The Design of Low Noise Amplifiers in Deep Submicron CMOS Processes: A Convex Optimization Approach

<div>White noise factor <svg height="9.39034pt" id="M157" style="vertical-align:-3.42943pt" version="1.1" viewbox="-0.0498162 -5.96091 6.63704 9.39034" width="6.63704pt" xmlns="http://www.w3.org/2000/svg" xmlns:xlink="http://www.w3.org/1999/xlink"><g transform="matrix(.013,0,0,-0.013,0,0)"><path d="M478 372C478 418 458 448 431 448C409 448 389 431 389 410C389 404 391 400 394 395C398 388 406 371 406 348C406 253 308 122 251 51H249C254 122 249 257 231 336C212 421 189 448 159 448C126 448 75 412 23 327L48 306C83 354 103 371 115 371C125 371 134 360 144 334C185 224 192 64 183 -19C146 -100 116 -202 110 -244L125 -261C154 -259 208 -234 222 -220C222 -194 225 -84 235 -23C247 -3 273 36 308 79C379 165 478 288 478 372Z" id="g113-225"></path><glyph.data ascent="3473" descent="-2876" horiz-adv-x="501" vert-adv-y="501"></glyph.data></g></svg> versus gate length.</div>

VLSI Design

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Figure 7

Figure 7: The Design of Low Noise Amplifiers in Deep Submicron CMOS Processes: A Convex Optimization Approach 