VLSI Design

Volume 2016, Article ID 3191286, 14 pages

http://dx.doi.org/10.1155/2016/3191286

## Shared Reed-Muller Decision Diagram Based Thermal-Aware AND-XOR Decomposition of Logic Circuits

Department of Electronics & Communication Engineering, National Institute of Technology Agartala, Agartala, Barjala, Jirania, Tripura 799046, India

Received 15 December 2015; Accepted 29 March 2016

Academic Editor: Jose Carlos Monteiro

Copyright © 2016 Apangshu Das and Sambhu Nath Pradhan. This is an open access article distributed under the Creative Commons Attribution License, which permits unrestricted use, distribution, and reproduction in any medium, provided the original work is properly cited.

#### Abstract

The increased number of complex functional units exerts high power-density within a very-large-scale integration (VLSI) chip which results in overheating. Power-densities directly converge into temperature which reduces the yield of the circuit. An adverse effect of power-density reduction is the increase in area. So, there is a trade-off between area and power-density. In this paper, we introduce a Shared Reed-Muller Decision Diagram (SRMDD) based on fixed polarity AND-XOR decomposition to represent multioutput Boolean functions. By recursively applying transformations and reductions, we obtained a compact SRMDD. A heuristic based on Genetic Algorithm (GA) increases the sharing of product terms by judicious choice of polarity of input variables in SRMDD expansion and a suitable area and power-density trade-off has been enumerated. This is the first effort ever to incorporate the power-density as a measure of temperature estimation in AND-XOR expansion process. The results of logic synthesis are incorporated with physical design in CADENCE digital synthesis tool to obtain the floor-plan silicon area and power profile. The proposed thermal-aware synthesis has been validated by obtaining absolute temperature of the synthesized circuits using HotSpot tool. We have experimented with 29 benchmark circuits. The minimized AND-XOR circuit realization shows average savings up to 15.23% improvement in silicon area and up to 17.02% improvement in temperature over the sum-of-product (SOP) based logic minimization.

#### 1. Introduction

With the rapid increase in the functional complexity and miniaturization of chips, power-density is becoming a critical concern in VLSI design and synthesis methodologies. Feature size scaling to meet the demand of the portability and performance issues increased the total power utilization of the chip. Consequently, the power-density becomes extensive and generates a thermal effect, which reduces the performance and efficiency of the circuit. Even the integrated circuit (IC) chip may burn out due to thermal runaway. In recent time, power-density is an important constraint for designing the VLSI circuits to reduce the thermal effect, because power-density directly converges to temperature [1]. So, optimized realization of a circuit taking power-density as a parameter in cost is very much important to limit the temperature generation. Temperature was given importance by researchers in physical design domain, but the cooling cost became high. With the high performance processors, the cooling solutions are rising at 1–3 or more per watt of power dissipation [2, 3]; this shows that cooling costs are increased exponentially with the increase of power-density. So, design-time thermal-aware techniques can be used to improve the power and thermal characteristics of integrated circuits.

Logic minimization plays an important role in combinational synthesis domain to optimize the circuit by increasing the shared logic within the functions. Once the minimized circuit is obtained, it is the switching activity and transition probabilities of the logic (dynamic power) that determine the power consumption in the circuit. Then, the power-density is obtained by taking the ratio of the power consumption and the utilized chip area. Here, in this paper, we have proposed a logic synthesizer which tries to optimize the chip area and power-density by providing trade-offs between the two and tries to reduce the thermal effect of the combinational logic circuits.

Multioutput function optimization aims at reducing the circuit area by extracting common subexpressions within the subfunctions. The most popular CAD tool packages which utilize the above logic are Espresso [4], SIS [5], and ABC [6]. Espresso targeted AND-OR based PLA structure and is more commonly known as two-level minimizer. On the other hand, SIS and ABC utilize multilevel logic circuits to increase the sharing between subfunctions. The logic implementation reported in [4, 5, 7] utilizes AND-OR realization to reduce the circuit area. However, in many real-life circuits used in the fields of coding theory, telecommunication, linear system, computer arithmetic coding circuits, error detection-correction circuits, and data encryption and decryption circuits are inherently the basic functions of mod-2 sum form. In such cases, AND-XOR minimized algorithms often produce more compact circuit than the AND-OR based realizations. AND-XOR based PLA realization offers higher testability than AND-OR based circuits. However, applications of AND-XOR based circuits have so far not become popular due to the following two obstacles:(i)XOR gates have slow speed and require large silicon area to realize in comparison with OR gates.(ii)The problem of optimization of AND-XOR functions is difficult although there has been a great deal of research in recent years.

With the development of new technologies and the advent of various field programmable gate array (FPGA) devices, the first obstacle has been solved. In programmable devices, the XOR gate is either easily realized in “universal modules” or directly available. For example, ATMEL FPGA series AT6000 uses two various input gates such as XORs, ANDs, and NANDs to configure logic blocks [8]. Regarding the second obstacle, more recently, there has been some success in achieving area reduction by employing optimization techniques specifically targeted towards initial AND/XOR representations in the well known Reed-Muller (RM) form.

In order to develop an AND-XOR based circuits realization, there are several types of expressions such as positive polarity Reed-Muller (PPRM), fixed polarity Reed-Muller (FPRM), pseudo Reed-Muller, generalized Reed-Muller, XOR sum of products, and Kronecker and pseudo Kronecker forms [9]. Each of these circuits has its own advantages. As far as XOR synthesis is concerned, this paper concentrates on the synthesis of FPRM circuits only.

In the above background, the problem of the current work can be addresses as follows.

A multi-input, multioutput Boolean function and weight factors perform FPRM decomposition and share the product terms. Minimization depending on weighted sum approach for area (number of product terms) and power-density is performed. The circuit realization is carried up to physical design synthesis to obtain the actual area and temperature.

The rest of the paper is organized as follows. Section 2 illustrates the motivation and previous work on AND-XOR synthesis. Section 3 presents thermal-aware AND-XOR problem formulation and synthesis approach. Section 4 illustrates the GA formulation for thermal-aware SRMDD based AND-XOR network synthesis. Section 5 presents experimental results and finally Section 6 draws the conclusion and future works.

#### 2. Motivation and Previous Works

The motivation of AND-XOR realization comes from Example 1.

*Example 1. *Consider a Boolean function consisting of 3-input and 2-output functions consisting of the following subfunctions:By realization of function using AND-OR network, it requires 4 product terms: , , , and . If we realize the same function using AND-XOR network with all positive polarities, it will provide 3 product terms. The FPRM forms of and subfunctions areThe Reed-Muller (RM) canonical expansion of a -variable Boolean function can be represented by terms. The general expansion of RM is given bywhere . All input variables appear in positive polarities in the expansion. Several modified versions of this basic canonical form have been studied. If the variables are allowed to take both positive and negative polarities, this is known as generalized Reed-Muller (GRM) form. Any arbitrary Boolean function can be expanded to represent it into AND-XOR network by deriving the Davio expansions [11]. The expansions arewhere and are called the cofactor of .

If we decompose the function using Shannon’s Expansion, three gates are required (two ANDs and one XOR), whereas only two gates (one AND and one XOR) are required to realize the same function using positive Davio (pD) or negative Davio (nD). In this work, we are applying the positive Davio expansion or negative Davio expansion to the given function using either positive or negative polarity of variables but not both for each variable. Then, the Boolean function is logically expressed as fixed polarity Reed-Muller (FPRM) expansion. For an -variable function, there are at most different FPRMs. The minimization problem is to find one with the minimum products among possible FPRMs. To solve the above problem, we have applied a Genetic Algorithm (GA) based formulation to identify the best polarity assignment to the input variables to get the desired output.

Detailed descriptions of two-level AND-XOR network synthesis have been done in [12, 13]. Better and minimized realization can be possible using AND-XOR logic synthesis compared with that of AND-OR synthesis in terms of fewer product terms and that has been reported by Sasao and Besslich in [14] and Ye and Roy in [15]. Sasao et al. deal with the problem of minimizing the two-level AND-XOR PLAs by utilizing both positive and negative polarity of variables and proposed several heuristic methodologies in mod-2 SOPs in [14, 16]. Realization of Boolean functions in the positive polarity AND-XOR form has long been proposed as Reed-Muller expansion in [17]. The modified versions of this basic canonical form have been studied by several researchers as time passes. The representation in which a variable can have either positive or negative polarity throughout the function is known as fixed polarity Reed-Muller (FPRM) form as given by Davio and Deschamps [18]. FPRM expansion utilizes a much smaller number of product terms than the original Reed-Muller form with high testability. An FPRM based heuristic approach has been proposed by Sarabi and Perkowski to find out the best polarity assignment [19]. A GA based polarity selection of FPRM realization scheme for multioutput Boolean function to minimize the area was presented by Chattopadhyay et al. in [12]. Low-power decomposition of XOR based synthesis has been presented by Narayanan and Liu [10]. In [13], a GA based area power trade-off analysis has been reported by Pradhan and Chattopadhyay. Elaborated survey of the work done so far has been given in [20]. However, all the above works did not consider the power-densities as a coefficient of estimating temperature of AND-XOR based circuits to analyze the thermal effect. We have contributed a trade-off analysis by taking power-density along with area. In logic synthesis level absolute value of temperature is unknown, so to evaluate temperature we have to consider power-density for temperature from the following equation. Temperature is directly proportional to power-density and this can be established by [21]In (5), is the average chip temperature. is the ambient temperature ( = 25°C). is the equivalent thermal resistance of the substrate (Si) layer plus the package and heat sink (cm^{2}·°C/W). (in W) is the total power consumption. (in cm^{2}) is the chip area.

Keeping ambient temperature constant in (5), it can be concluded that temperature generation depends only on power and area (since equivalent thermal resistance is constant for a particular substrate). This has led us to consider power-density as the constraint of temperature and subsequently consider power-density minimization along with area during polarity selection of FPRM based AND-XOR network synthesis of circuits.

#### 3. Thermal-Aware AND-XOR Problem Formulation and Synthesis Approach

To represent a Boolean function efficiently into FPRM, the critical issue is to select the polarity thoughtfully for maximum sharing considering the optimization parameters. In this section, we have explained the method for assigning the input variable polarity and calculation of area and power-density depending on polarity assigned.

-input, -output Boolean function can be realized as an FPRM expansion by maintaining each variable with a fixed polarity, either positive or negative throughout the expansion. A variable appears either in true or in complemented form within the expansion. This can be achieved by the following steps:(i)Boolean functions are expressed into disjoint cube representation.(ii)Without affecting the functionality, ORs are replaced with XORs.(iii)Each variable is assigned with consistent polarity for FPRM representation.(iv)Decompose the literals into a consistent polarity one.

The output subfunctions are represented into AND-OR cubes into Boolean functions. The AND-OR cubes are converted to a set of disjoint cubes. Then, without affecting the functionality, the ORs can be replaced with XORs. After obtaining the set of AND-XOR cubes, the next task is to determine the polarity assignment. The polarity can be assigned as to the variables to maximize the sharing of product terms to obtain the desired output of the FPRM realization. A variable with polarity 1 occurs in true form in all product terms, whereas variable with polarity 0 occurs only in complemented form. To obtain the FPRM form, the literals having polarities different from that assigned to the corresponding variables are replaced by () if input variable polarity is 1. Otherwise, the variable is . Depending on the polarity, the Boolean function gets represented in different FPRM realization. Each realization provides a different area in the form of a number of product terms and respective power-densities and allows a trade-off between the two. Example 2, in Section 3.1, explains the area computation which is preceded by power-density estimation.

##### 3.1. Shared Reed-Muller Decision Diagram (SRMDD) Decomposition Based on Fixed Polarity and Area Computation

Shared decision diagrams are used to represent multioutput Boolean functions, likewhere and and denote the number of input and number of output variables, respectively. different logic functions are decomposed into AND-XOR based realization by maintaining a fixed polarity. The realized functions share the identical terms, which are represented by a common part of the SRMDD. In this paper, the shared FPRMs within the subfunctions are termed SRMDD. By iteratively applying FPRM decomposition and sharing the identical product terms, we obtain a compact SRMDD. Example 2 shows the formation of SRMDD of the full-adder circuit.

Subsequently, area computation has been illustrated.

*Example 2. *In full-adder circuit, , , and are the three inputs added to produce the “Sum” and “Carry” outputs. The functions are given byBoth output functions can be realized as FPRM based AND-XOR network by applying the positive Davio expansion to and and negative Davio to . and appear as true form and appears as complemented form by substituting , , and into the output functions Sum and Carry. After decomposition, we have The identical product terms, such as , , , and , are shared between the two output functions.

Figure 1 illustrates the formation of FPRM expansion tree of Sum function. The nodes with pD denote the positive Davio expansions, and the nodes with nD denote the negative Davio expansions. In each path from the root node to constant 1, the logical product of the labels in the path corresponds to a product term in an FPRM. Figure 2 shows the FPRM expansion tree for Carry function. After sharing the identical product terms, the SRMDD tree of Sum and Carry generates 6 product terms, whereas if we expand the tree separately it would require 10 product terms. The product terms are the representative area for the Boolean functions. By changing the polarity of a variable in a given function, the structure of the circuit is changed. Initially, the circuit was in the form of AND-OR circuit. After polarity assignment, the circuit is represented in the form of AND-XOR circuit. But the functionality of both structures is the same. In particular, the set of input responses of both circuits is the same. So, the truth vector formed in AND-XOR may differ from its primary initial AND-OR realization keeping the functionality unchanged. In Reed-Muller AND-XOR realization chance of sharing product terms among the subfunction increases, which results in area reduction.