Table of Contents
VLSI Design
Volume 2016, Article ID 3191286, 14 pages
http://dx.doi.org/10.1155/2016/3191286
Research Article

Shared Reed-Muller Decision Diagram Based Thermal-Aware AND-XOR Decomposition of Logic Circuits

Department of Electronics & Communication Engineering, National Institute of Technology Agartala, Agartala, Barjala, Jirania, Tripura 799046, India

Received 15 December 2015; Accepted 29 March 2016

Academic Editor: Jose Carlos Monteiro

Copyright © 2016 Apangshu Das and Sambhu Nath Pradhan. This is an open access article distributed under the Creative Commons Attribution License, which permits unrestricted use, distribution, and reproduction in any medium, provided the original work is properly cited.

Citations to this Article [4 citations]

The following is the list of published articles that have cited the current article.

  • Xuejiao Ma, and Yinshui Xia, “Power optimization based on dual-logic using And-Xor-Inverter Graph,” 2017 IEEE 12th International Conference on ASIC (ASICON), pp. 351–354, . View at Publisher · View at Google Scholar
  • Apangshu Das, Akash Debnath, and Sambhu Nath Pradhan, “Area, power and temperature optimization during binary decision diagram based circuit synthesis,” 2017 Devices for Integrated Circuit (DevIC), pp. 778–782, . View at Publisher · View at Google Scholar
  • Zhen-Xue He, Li-Min Xiao, Li Ruan, Fei Gu, Zhi-Sheng Huo, Guang-Jun Qin, Ming-Fa Zhu, Long-Bing Zhang, Rui Liu, and Xiang Wang, “A Power and Area Optimization Approach of Mixed Polarity Reed-Muller Expression for Incompletely Specified Boolean Functions,” Journal of Computer Science and Technology, vol. 32, no. 2, pp. 297–311, 2017. View at Publisher · View at Google Scholar
  • Chuandong Chen, Bing Lin, and Michelle Zhu, “Verification method for area optimization of mixed-polarity Reed-Muller logic circuits,” Journal of Engineering Science and Technology Review, vol. 11, no. 1, pp. 28–34, 2018. View at Publisher · View at Google Scholar