Shared Reed-Muller Decision Diagram Based Thermal-Aware AND-XOR Decomposition of Logic Circuits

Table 4

Postsynthesis analysis of SRMDD.

Benchmark; circuits	= 0, = 1		= 0.6, = 0.4		= 1, = 0		Max_Delay (nS)	CPU time (s)
	Area (µm^2)	PD (nW/m^2)	Area (µm^2)	PD (nW/m^2)	Area (m^2)	PD (nW/m^2)
5xp1	136	14.26	122	14.46	122	14.46	0.73	7
alu2	610	10.53	523	13.43	523	13.43	1.10	7
apex4	2790	13.25	2790	13.25	2790	13.25	1.99	9
clip	238	13.07	238	13.07	238	13.07	0.52	7
cm82a	12	13.76	7	14.03	7	14.03	0.28	6
cm162a	87	16.82	62	17.60	56	18.30	0.49	6
cm163a	104	12.00	45	14.47	28	15.04	0.56	7
duke2	379	10.21	255	12.86	255	12.86	1.18	7
ex5	397	11.29	397	11.29	189	14.73	0.78	7
f51m	132	15.16	131	15.36	131	15.36	0.55	7
inc	146	12.85	143	13.15	122	17.47	0.53	7
lal	125	12.39	125	12.39	125	12.39	0.71	7
misex1	88	10.88	69	12.56	57	13.75	0.68	6
pbo2	179	11.14	152	12.89	152	12.89	0.56	7
pcler8	156	9.46	142	11.54	142	11.54	0.49	7
rd53	33	14.42	26	12.89	26	12.89	0.37	6
rd73	93	19.21	93	19.21	93	19.21	0.34	6
shiftc	101	15.11	101	15.11	101	15.11	0.42	7
sqrt8	96	16.39	96	16.39	96	16.39	0.61	6
squar5	73	12.62	53	15.11	53	15.11	0.32	6
tcon	36	9.58	36	9.58	27	11.73	0.22	6
ttt2	147	14.76	137	15.46	137	15.46	0.54	7
x2	58	12.12	39	16.95	39	16.95	0.46	6
xor5	5	12.87	5	12.87	5	12.87	0.11	6
z4ml	18	12.68	18	12.68	18	12.68	0.32	6
Z5xp1	130	12.88	130	12.88	130	12.88	0.64	7
o64	98	12.46	91	11.36	86	10.07	0.73	9
apex5	561.6	8.13	561.6	8.13	561.6	8.13	1.10	15
x3	612.32	10.42	556.12	11.25	510.2	11.83	1.99	14