Shared Reed-Muller Decision Diagram Based Thermal-Aware AND-XOR Decomposition of Logic Circuits

<table class="table-group" id="tab5"><tr><td><table class="table"><tr><td class="thead-hr" colspan="3"><hr/></td></tr><tr class="thead"><td class="align_left"><svg height="9.14241pt" id="M195" style="vertical-align:-3.1815pt" version="1.1" viewbox="-0.0498162 -5.96091 14.0106 9.14241" width="14.0106pt" xmlns="http://www.w3.org/2000/svg" xmlns:xlink="http://www.w3.org/1999/xlink"><g transform="matrix(.013,0,0,-0.013,0,0)"><path d="M689 332C689 394 670 448 646 448C620 448 597 421 597 396C597 386 600 381 608 372C619 359 620 334 620 315C620 150 538 45 454 45C414 45 386 67 386 122C386 138 388 158 394 180L457 426L452 432L377 416L315 156C302 100 259 45 216 45C176 45 148 67 148 122C148 133 152 158 156 180C162 212 173 259 194 332C201 357 206 384 206 405C206 430 198 448 174 448C125 448 66 406 23 342L43 319C84 368 110 383 121 383C126 383 128 382 128 377C128 370 127 359 122 343C99 268 84 204 77 156C74 137 70 111 70 104C70 25 125 -12 180 -12C228 -12 276 12 319 50C338 8 378 -12 418 -12C549 -12 689 166 689 332Z" id="g113-120"></path><glyph.data ascent="3473" descent="-2876" horiz-adv-x="712" vert-adv-y="712"></glyph.data></g><g transform="matrix(.0091,0,0,-0.0091,8.931,3.132)"><path d="M389 0V32C297 38 291 46 291 118V635C234 613 175 595 109 583V556L161 554C203 552 207 547 207 497V118C207 46 201 38 110 32V0H389Z" id="g50-50"></path><glyph.data ascent="3443" descent="-2856" horiz-adv-x="487" vert-adv-y="487"></glyph.data></g></svg>,  <svg height="9.14241pt" id="M196" style="vertical-align:-3.1815pt" version="1.1" viewbox="-0.0498162 -5.96091 14.0106 9.14241" width="14.0106pt" xmlns="http://www.w3.org/2000/svg" xmlns:xlink="http://www.w3.org/1999/xlink"><g transform="matrix(.013,0,0,-0.013,0,0)"><path d="M689 332C689 394 670 448 646 448C620 448 597 421 597 396C597 386 600 381 608 372C619 359 620 334 620 315C620 150 538 45 454 45C414 45 386 67 386 122C386 138 388 158 394 180L457 426L452 432L377 416L315 156C302 100 259 45 216 45C176 45 148 67 148 122C148 133 152 158 156 180C162 212 173 259 194 332C201 357 206 384 206 405C206 430 198 448 174 448C125 448 66 406 23 342L43 319C84 368 110 383 121 383C126 383 128 382 128 377C128 370 127 359 122 343C99 268 84 204 77 156C74 137 70 111 70 104C70 25 125 -12 180 -12C228 -12 276 12 319 50C338 8 378 -12 418 -12C549 -12 689 166 689 332Z" id="g113-120"></path><glyph.data ascent="3473" descent="-2876" horiz-adv-x="712" vert-adv-y="712"></glyph.data></g><g transform="matrix(.0091,0,0,-0.0091,8.931,3.132)"><path d="M414 144C384 79 371 75 317 75H135L276 221C367 316 408 376 408 465C408 570 327 635 237 635C179 635 131 609 100 575L42 494L67 471C94 510 138 565 205 565C277 565 321 517 321 435C321 348 258 270 195 195C146 137 88 81 33 26V0H411C423 44 433 88 446 135L414 144Z" id="g50-51"></path><glyph.data ascent="3443" descent="-2856" horiz-adv-x="487" vert-adv-y="487"></glyph.data></g></svg></td><td class="align_center">Average % increase with respect to min. area</td><td class="align_center">Average % increase with respect to min. Pow_den</td></tr><tr><td class="thead-hr" colspan="3"><hr/></td></tr><tr><td class="align_left">0, 1</td><td class="align_center">30.18</td><td class="align_center">1.00</td></tr><tr><td class="align_left">0.6, 0.4</td><td class="align_center">9.24</td><td class="align_center">6.61</td></tr><tr><td class="align_left">1, 0</td><td class="align_center">1.00</td><td class="align_center">10.11</td></tr><tr class="table-tr"><td colspan="3"><hr class="tbody-hr"/></td></tr></table></td></tr></table>

Postsynthesis area power-density trade-off.

VLSI Design

tab5

Table 5

Table 5: Shared Reed-Muller Decision Diagram Based Thermal-Aware AND-XOR Decomposition of Logic Circuits 