Research Article  Open Access
Improved Switching Energy Reduction Approach in LowPower SAR ADC for Bioelectronics
Abstract
Lowpower analogtodigital converter (ADC) is a crucial part of wearable or implantable bioelectronics. In order to reduce the power of successiveapproximationregister (SAR) ADC, an improved energyefficient capacitor switching scheme of SAR ADC is proposed for implantable bioelectronic applications. With sequence initialization, novel logic control, and capacitive subconversion, 97.6% switching energy is reduced compared to the traditional structure. Moreover, thanks to the topplate sampling and capacitive subconversion, 87% inputcapacitance reduction can be achieved over the conventional structure. A 10bit SAR ADC with this proposed switching scheme is realized in 65 nm CMOS. With 1.514 KHz differential sinusoidal input signals sampled at 50 KS/s, the ADC achieves an SNDR of 61.4 dB and only consumes power of 450 nW. The area of this SAR ADC IP core is only 136 μm × 176 μm, making it also areaefficient and very suitable for biomedical electronics application.
1. Introduction
With the feature size of integrated circuits downscaled to nanoscale, the integration level of SystemonChip (SoC: SystemonChip) has been increased dramatically. For some special applications, such as batterypowered or wirelesspowered implantable bioelectronics, lowpower consumption and miniaturized size have become the key factors of the system. In these applications, the successiveapproximationregister (SAR) ADCs, especially charge scaling SAR ADCs, are prevalent options for lowpower A/D conversion. Recently, many publications are about the research on reducing the switching power of the D/A network in SAR ADC [1–8]. In [1], energy saving is achieved by splitting the mostsignificant bit (MSB) into several binary scaled capacitors. Monotonic downward switching scheme is proposed in [2], while is used in [3] for energy reduction. based and monotonic switching are combined; hence more energy is saved in [4]. For the switching scheme in [5], no energy is consumed during generating the first 3 bits, making it more energyefficient. Moreover, the method in [6] also achieves very low switching energy by using multiple references and sequence initialization. However, the static power consumed during generating these additional subreferences diminishes its attraction. In this paper, an improved energyefficient capacitor switching procedure for charge scaling SAR ADC is proposed. Instead of the resistive subreference generator used in [6], capacitive subconversion is used to generate the last 2 bits without any static power. For powerefficiency, area reduction, and easy realization in CMOS process, two 1bit capacitor arrays are combined to generate the last 2 bits. This innovation comes from the attenuation capacitor based dualarray charge scaling structure [7], in which the attenuation capacitor would be an integral multiple of unit capacitor, , only when the LSB array just converts 1 bit [8]. Moreover, to verify the applicability of this proposed scheme, a 10bit 50 KS/s SAR ADC that can be used in multichannel neural recording implant is realized in 65 nm CMOS. The application of this proposed SAR ADC in multichannel neural recording analog frontend is shown in Figure 1.
The rest of this paper is organized as follows. Section 2 shows the proposed switching scheme. The switching energy analysis and comparison are provided in Section 3. In Section 4, the design results of a 10bit SAR ADC with this proposed scheme are given. Finally, Section 5 concludes this paper.
2. Proposed Switching Procedure
Figure 2 illustrates the proposed scheme in detail for a 5bit SAR A/D conversion, which is realized by differential 2bit capacitor arrays. Different from [6], subreferences , , and are generated capacitively for powerefficiency improvement.
(a)
(b)
During the sampling phase, the topplates of these two differential capacitor arrays are connected to and separately, while the connection of the bottomplates is initiated to “0 1 1 1 1.” This means the bottomplate of the mostsignificant bit (MSB) capacitor is set to ground (Gnd), and these bottomplates of the other capacitors are connected to . The sampling switches turn off and the first comparison starts at the end of the sample phase to generate the MSB. The switching energy consumed in each conversion step is shown in Figure 2. Thanks to the topplate sampling, there is no switching energy taken from reference during the MSB generation. After the MSB is determined, the MSB capacitor on the lower voltage potential side is switched to to produce the 2nd bit. Since all these bottomplates of this capacitor array are connected to the same DC voltage, , still no switching energy is taken from in the production of the 2nd bit. Once the 2nd bit is produced, the monotonic switching presented in [2] will be utilized in the subsequent conversion. According to [6], an improvement over [2] is that the variation of input commonmode voltage of the comparator can be reduced because of increase on the lower voltage potential side during the 2nd generation.
Figure 2(b) shows the generation of the last 2 bits in the proposed conversion. Since the operation of the proposed scheme is symmetrical, which can be seen from Figure 2(a), A1–B2 is used for this description. Additional reference voltage levels (, , and ) are needed. For energy reduction, we introduce a capacitive method, which is similar to a segmented charge redistribution conversion, to generate these subreferences. As shown in Figure 2(b), each segmented subarray is only used to generate 1 bit. Then, these two attenuation capacitors would be , making the process realization and matching of the subarray easier than a normal 2bit array, in which the attenuation capacitor should be a nonintegral multiple of unit capacitor, .
3. Switching Energy Analysis
The behavioral simulation in Matlab was performed for 10bit SAR ADCs with different switching schemes. In the proposed scheme, 10bit resolution is realized by a “7 + 1 + 1” 3step segmented capacitor array. Figure 3 plots the switching energy versus digital code. Compared to the conventional architecture, the average energy and total capacitance of the proposed scheme are reduced by 97.6% and 87%, respectively.
Table 1 shows the comparison of different schemes with respect to the average switching energy and the capacitor array area. Compared with previous twolevel schemes [1, 2], the proposed switching procedure is more efficient in energy and area. Compared with these schemes in [3–6], the advantage of this proposed scheme is twolevel switching. This is similar to that in [1, 2], but the energy consumption has been dramatically reduced. For comprehensive comparison with the scheme proposed in [6], we also consider the static power consumed by the resistive subreference generator, which is only used for generating the last two bits. If the intermittentmode reference generator proposed in [6] is utilized, the static power of the resistor string would be , where represents the total resistance of the resistor string and is used to represent the poweron duty cycle of the intermittent reference generator. For biomedical application such as multichannel neural recording systems, if each recording channel has its own inchannel ADC, at least 20 KS/s sampling rate is needed for each ADC. Taking a 10bit SAR ADC with 50 fF unit capacitor as an example, should be around 100 KΩ for settling requirement. Taking for 10bit A/D conversion with 10 clock cycles and V, the static power consumed by the subreference generator is 2 μW, much more than nWlevel switching power of the capacitor array. Obviously, significant improvement has been achieved in the proposed switching scheme over that in [6].

4. 10Bit SAR ADC with the Proposed Scheme
Shown in Figure 4 is the architecture of a 10bit SAR ADC with the proposed switching scheme. This fully differential SAR ADC is composed of sample switches, capacitor arrays, dynamic comparator, and SAR logic. Besides the proposed switching procedure in Section 2, dynamic comparator is also used in this design for power reduction [2]. To improve the switch linearity, bootstrapped switches are utilized to fix the gatesource voltages of the sampling MOSFETs at a constant voltage level [2].
In the structure proposed in Figure 5, combined structure acts as the subconversion to generate subreferences , , and . The attenuation capacitor is an integral multiple of unit capacitor, , which facilitates the matching to some extent in the layout design. However, the DC performance is sensitive to the parasitic capacitance of the attenuation capacitor, which has been proved in [7]. As shown in Figure 5, parasitic capacitance, , between the topplate of and substrate will result in gain error of the ADC. Since it cannot affect the capacitors’ binary ratio, it will not cause any nonlinearity. In Figure 5, is composed of the topplate parasitic capacitance of and and the bottomplate parasitic capacitance of , while is made up of the topplate parasitic capacitance of and and the bottomplate parasitic capacitance of . These two parasitic capacitors, and , will lead to nonlinearity of SAR ADC, because they can affect the equivalent capacitance of the subconversion array. However, the subconversion array is only used to generate the last 2bit output of the ADC, so the requirement for the accuracy of these subreferences is not too stringent.
A 10bit SAR ADC with this proposed switching scheme is realized in a 65 nm CMOS process. To analyze the effect of parasitic capacitance on the ADC performance, comparison is made from the simulated results in Figure 6. Shown in Figure 6(a) is the simulation result of a 10bit ADC without any parasitic capacitance in the capacitor array, while Figure 6(b) shows the simulation result with 10% bottomplate parasitic capacitance and 5% topplate parasitic capacitance. There is only 2 dB decrease in the SNDR, which would be acceptable for a 10bit ADC.
(a)
(b)
This 10bit SAR ADC IP core occupied a total active area of 136 μm × 176 μm. MetalOxideMetal (MOM) capacitors are used in this ADC. To improve the matching performance and make the input noise much less than the quantization noise, the unit capacitance is selected to be 32.3 fF. Each capacitor array has 134 unit capacitors. Therefore, the input capacitance of each capacitor array is around 4.3 pF. Furthermore, during the layout design, these capacitors in the subarray are carefully placed and connected to reduce the effect of and on the linearity performance of the ADC. Shown in Figure 7 is the simulated linearity performance of this 10bit SAR ADC with proposed switching procedure. The differential nonlinearity (DNL) is 0.61 LSB/−0.92 LSB, and the integral nonlinearity (INL) is ±0.88 LSB. When 1.514 KHz differential sinusoidal input signals are sampled at 50 KS/s, the ADC achieves an SNDR of 61.4 dB. The power consumption is less than 450 nW. The FigureofMerit (FoM) is around 9.5 fJ/conversion step.
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5. Conclusion
An improved energyefficient capacitor switching scheme has been presented for lowpower SAR ADC in implantable bioelectronic applications. By using capacitive subconversion, this proposed twolevel scheme achieved higher resolution, smaller area, and higher energyefficiency, compared with other twolevel schemes in previous works. Compared to the conventional scheme, over 97.6% of average switching energy and about 87% of unit capacitors in the capacitor array have been reduced. The superiority and applicability of this proposed switching scheme were also proven by the realization of a 10bit 65 nm CMOS SAR ADC.
Competing Interests
The authors declare that they have no competing interests.
Acknowledgments
This work has been partly supported by the National Science and Technology Important Project of China (no. 2016ZX03001003006), the Natural Science Foundation of China (no. 61674122), the Natural Science Foundation of Shaanxi Province (no. 2014JQ8332), and the Special Scientific Research Foundation of Shaanxi Education Department in China (no. 16JK1705).
References
 B. P. Ginsburg and A. P. Chandrakasan, “An energyefficient charge recycling approach for a SAR converter with capacitive DAC,” in Proceedings of the IEEE International Symposium on Circuits and Systems (ISCAS '05), vol. 43, pp. 184–187, IEEE, May 2005. View at: Publisher Site  Google Scholar
 C.C. Liu, S.J. Chang, G.Y. Huang, and Y.Z. Lin, “A 10bit 50MS/s SAR ADC with a monotonic capacitor switching procedure,” IEEE Journal of SolidState Circuits, vol. 45, no. 4, pp. 731–740, 2010. View at: Publisher Site  Google Scholar
 Y. Zhu, C.H. Chan, U.F. Chio et al., “A 10bit 100MS/s referencefree SAR ADC in 90 nm CMOS,” IEEE Journal of SolidState Circuits, vol. 45, no. 6, pp. 1111–1121, 2010. View at: Publisher Site  Google Scholar
 Z. Zhu, Y. Xiao, and X. Song, “V_{CM}based monotonic capacitor switching scheme for SAR ADC,” Electronics Letters, vol. 49, no. 5, pp. 327–329, 2013. View at: Publisher Site  Google Scholar
 X. Tong and M. Ghovanloo, “Energyefficient switching scheme in SAR ADC for biomedical electronics,” Electronics Letters, vol. 51, no. 9, pp. 676–678, 2015. View at: Publisher Site  Google Scholar
 X. Y. Tong, W. P. Zhang, and F. X. Li, “Lowenergy and areaefficient switching scheme for SAR A/D converter,” Analog Integrated Circuits and Signal Processing, vol. 80, no. 1, pp. 153–157, 2014. View at: Publisher Site  Google Scholar
 Z. Zhu, Z. Qiu, M. Liu, and R. Ding, “A 6to10bit 0.5Vto0.9V reconfigurable 2MS/s power scalable SAR ADC in 0.18μm CMOS,” IEEE Transactions on Circuits and Systems I: Regular Papers, vol. 62, no. 3, pp. 689–696, 2015. View at: Google Scholar
 H. Wang and Z. Zhu, “Energyefficient and referencefree monotonic capacitor switching scheme with fewest switches for SAR ADC,” IEICE Electronics Express, vol. 12, no. 7, 2015. View at: Publisher Site  Google Scholar
Copyright
Copyright © 2016 Xingyuan Tong and Tiantian Sun. This is an open access article distributed under the Creative Commons Attribution License, which permits unrestricted use, distribution, and reproduction in any medium, provided the original work is properly cited.