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VLSI Design
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Special Issues
VLSI Design
/
2016
/
Article
/
Tab 3
/
Research Article
A Cache System Design for CMPs with Built-In Coherence Verification
Table 3
Relationship between RMTs of cell
and cell
for next state computation.
RMT
of
th rule
RMTs
of
th rule
0/4
0, 1
1/5
2, 3
2/6
4, 5
3/7
6, 7
