New Proposal for MCML Based Three-Input Logic Implementation

Table 2

Effect of process variation on propagation delay and voltage swing of three-input MCML XOR gate designs.

XOR gate topology	NMOS	T	F	S	F	S
	PMOS	T	F	S	S	F
Propagation delay (ps)
Conventional		1178	976	1586	1091	1417
Topology 1		1049	971	1253	1071	1126
Topology 2		732	627	930	723	806
Proposed		614	430	664	659	661
Voltage swing (mV)
Conventional		400	444	290	580	264
Topology 1		400	434	286	572	250
Topology 2		400	454	296	576	256
Proposed		400	424	298	550	216