VLSI Design

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Research Article

State-Transition-Aware Spilling Heuristic for MLC STT-RAM-Based Registers

Table 4

A statistic study of two consecutive writes to registers of eight 2-bit MLLC STT-RAM cells.

Node Node Node

Old value000100010001011000011000101000010100000010000001
New value101011010001111000111000110000000000010011110001
Number of transactions
Statistics of transactions
 Soft transitions213
 Hard transitions421

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