Research Article
State-Transition-Aware Spilling Heuristic for MLC STT-RAM-Based Registers
Table 4
A statistic study of two consecutive writes to registers of eight 2-bit MLLC STT-RAM cells.
| | | Node | Node | Node |
| | Old value | 0001000100010110 | 0001100010100001 | 0100000010000001 | | New value | 1010110100011110 | 0011100011000000 | 0000010011110001 | | Number of transactions | | | | | ZT | 4 | 5 | 4 | | ST | 0 | 1 | 3 | | HT | 2 | 2 | 1 | | TT | 2 | 0 | 0 | | Statistics of transactions | | | | | Soft transitions | 2 | 1 | 3 | | Hard transitions | 4 | 2 | 1 |
|
|
