Novel Verification Method for Timing Optimization Based on DPSO
Timing optimization for logic circuits is one of the key steps in logic synthesis. Extant research data are mainly proposed based on various intelligence algorithms. Hence, they are neither comparable with timing optimization data collected by the mainstream electronic design automation (EDA) tool nor able to verify the superiority of intelligence algorithms to the EDA tool in terms of optimization ability. To address these shortcomings, a novel verification method is proposed in this study. First, a discrete particle swarm optimization (DPSO) algorithm was applied to optimize the timing of the mixed polarity Reed-Muller (MPRM) logic circuit. Second, the Design Compiler (DC) algorithm was used to optimize the timing of the same MPRM logic circuit through special settings and constraints. Finally, the timing optimization results of the two algorithms were compared based on MCNC benchmark circuits. The timing optimization results obtained using DPSO are compared with those obtained from DC, and DPSO demonstrates an average reduction of 9.7% in the timing delays of critical paths for a number of MCNC benchmark circuits. The proposed verification method directly ascertains whether the intelligence algorithm has a better timing optimization ability than DC.
Timing optimization for logic circuits is one of the most important requirements during logic synthesis [1–4]. The industry’s mainstream electronic design automation (EDA) tool for logic synthesis is Design Compiler (DC) produced by Synopsys®. Timing optimization algorithms for logic circuits have been integrated in DC and have been demonstrated to reduce critical path delays significantly [5, 6]. Figure 1 illustrates the positioning of logic circuits (represented by ellipses) between flip-flops FF1 and FF2 of a pipeline circuit [7, 8], where the logic circuits generally employ multiple inputs and outputs. As shown by the red line in the figure, a typical path, denoted as the critical path, for the process of timing optimization in DC begins from the clock pin of FF1, passes through logic circuits, and finally arrives at the D pin of FF2. Here, the clock pin of FF1 is the startpoint of the critical path, and the D pin of FF2 is the endpoint of the critical path.
To facilitate timing optimization, logic circuits with inputs and outputs are transformed to equivalent mixed polarity Reed-Muller (MPRM) [9, 10] circuits, which have mixed polarities. Abundant experimental data and conclusions are available regarding the timing optimization of an MPRM logic circuit based on intelligence algorithms. However, the experimental results of intelligence algorithms cannot be compared with those of mainstream EDA tools, thus making the verification of the superiority of intelligence algorithms over EDA tools impossible.
To address these problems, this research proposed a new related verification method. The suggested verification method allows for contrast analysis between the experimental results of an intelligence algorithm and the optimization outcomes of an EDA tool, thereby evaluating the optimization ability of the intelligence algorithm.
2. State of the Art
MPRM is a standard form of a logic circuit; the problem of timing-driven logic optimization for MPRM circuits is an nondeterministic polynomial (NP) time complete problem . The discrete particle swarm optimization (DPSO) algorithm [12–15], genetic algorithm (GA) [16, 17], and simulated annealing (SA) [18–20] are commonly employed methods for solving the timing optimization of MPRM logic circuits.
On the basis of research on discrete ternary particle swarm optimization, Yu et al.  proposed a ternary diversity particle swarm optimization (TDPSO). A mathematic mode for area and low power dissipation was built and mixed polarity conversion of XNOR/OR circuits was improved. The algorithm was tested using MCNC benchmark circuits. Experimental results showed that the algorithm significantly outperformed the reported method. However, the experimental results were not compared with the optimization outcomes of the EDA tool. Thus, determining whether this algorithm is better than the EDA tool in terms of timing optimization is impossible.
To improve the efficiency of the polarity optimization of MPRM logic circuits, He et al.  proposed an efficient and fast polarity optimization approach (FPOA) considering the polarity conversion sequence. FPOA performed better for a complicated MPRM logic circuit. Nevertheless, experimental data on this algorithm were not compared with optimization outcomes of the EDA tool.
Zhang et al.  proposed an innovative niche GA for area optimization of fixed-polarity RM circuits. Experimental results of the MCNC benchmark circuits showed that the proposed algorithm was superior to the traditional GA. However, this study compared niche GA and traditional GA but did not compare the optimization results of the niche GA with those of the EDA tool.
Wang et al.  presented a power estimation model for MPRM logic circuits, which accurately and efficiently handled temporal signal correlations during the estimation of average power using lag-one Markov chains. An ordered binary decision diagram-based procedure was used to propagate the temporal correlations from the primary inputs throughout the network. Unfortunately, the experimental data of the model were impossible to compare with experimental data of the mainstream EDA tool.
Bu and Jiang  proposed a hybrid multivalued DPSO for the minimization problem of the MPRM logic circuit. Compared with the simulated annealing genetic algorithm (SAGA), this hybrid multivalued DPSO increased the time efficiency of MPRM minimization while achieving comparable optimization results. However, the experimental data were compared only with the optimization results of SAGA and not with the optimization results of the mainstream EDA tool.
Yang and Xu  suggested a whole annealing genetic algorithm (WAGA), which was used to search for MPRM functions for obtaining optimal circuit implementation. By combining the global searching ability of a GA and the local searching ability of SA, WAGA could achieve fast convergence. The algorithm was more effective than other GA methods in searching for the best MPRM functions. Nevertheless, experimental results were unable to prove the superiority of WAGA to the EDA tool.
Many studies are available on the timing optimization of MPRM logic circuits based on different intelligence algorithms. Their experimental results were mainly proposed based on intelligence algorithms. No verification method exists for comparing the timing optimization results of an EDA tool and an intelligence algorithm to determine whether an intelligence algorithm is superior to the EDA tool for timing optimization.
Accordingly, a novel verification method was designed in this study. We employ MCNC benchmark circuits in the Berkeley Logic Interchange Format (BLIF) and limit the logic gates that can be mapped in the technology library to two-input AND gates, two-input XOR gates, and inverters. First, the DPSO algorithm is applied for timing optimization of the MCNC benchmark circuits according to the BLIF netlist. Then, the benchmark circuits with BLIF format are transformed to the VHSIC Hardware Description Language (VHDL) format and then compiled in DC. The critical paths are then calculated according to the netlist saved in DC, and the timing optimization results are reported and compared with the results obtained from the DPSO algorithm.
3. The Proposed Method
In this section, a novel verification method is proposed. First, the MPRM circuit and its mathematical model are introduced. Second, the calculation equations for timing delay of a critical path with DPSO and with DC are proposed. Finally, the steps of the DPSO algorithm for timing optimization and the verification process are proposed.
3.1. MPRM Mathematic Model
The Boolean expression of -input combinational logic circuit is where is the logical OR operation of a set of variables; is the minterm coefficient; is the minterm ordinal, which can be expressed as ; is the minterm, which can be expressed as . The relationship between and its negation , collectively denoted as , and , is given as follows: An MPRM circuit with inputs has expansions, which can be expressed as follows:Here, is the input of the MPRM circuit. represents the polarity value of the MPRM and could be expressed as , where . It is a ternary system. is XOR; is the jth coefficient vector of MPRM; and is the th product item of the MPRM. Values of in term “AND” are shown in Table 1.
3.2. Timing Model
The single logic path among all paths that has the longest timing delay from the startpoint to the endpoint is denoted as the critical path. The timing optimization developed in this paper for logic circuits regards the critical path as the basic optimization target. Here, the startpoint of a logic path is taken as the clock pin of the front flip-flop, the endpoint is the input pin of the next flip-flop, and the circuits between the startpoint and the endpoint consist of logic gates.
Figure 2 illustrates the combinational logic circuits with inputs and outputs employed in the present study, where the inputs are and is one of the outputs. The logic circuit with endpoint can be expressed by (3). This combinational logic circuit can be decomposed into a logical network comprising two-input AND gates, two-input XOR gates, and inverters. When the logic of the MPRM circuit has been optimized using the DPSO algorithm, which ignores the timing delay for interconnected wires between the pins of logic gates, the corresponding maximum timing delay can be expressed aswhere represents the number of logic gates from any input to any output in the combinational logic circuits. For comparison, the same logic circuits are synthesized by DC, which also ignores the timing delay for interconnected wires between the pins of logic gates, and the logic gates that can be mapped to netlist in DC are limited to two-input AND gates, two-input XOR gates, and inverters. Finally, the logic circuit timing is constrained for optimization and mapped to the technology library in DC, and every logic gate in the critical path is defined as a timing delay unit. Thus, the maximum timing delay of the critical path obtained from DC can be defined as follows:where represents the total number of logic gates from the startpoint to the endpoint of the critical path, which can be calculated according to timing reports of the critical path generated by DC.
3.3. DPSO Algorithm
Particle swarm optimization (PSO) is a global optimal search algorithm based on swarm intelligence theory. Because of its simple process, few parameters, good convergence, and robustness, PSO has been commonly employed for addressing optimization problems. DPSO is an effective endmember extraction algorithm based on PSO with the advantage of more rapid convergence.
In the DPSO algorithm, the position and velocity of each particle in a swarm are initialized randomly in the solution space. Assuming that the total number of particles is in an -dimensional search space, the position of the th particle can be expressed as , and its flying velocity can be depicted as . In addition, the optimal position of particle is expressed as , and the optimal location of the swarm is expressed as . In addition, the update equations for the velocity and position of particle at the th iteration can be expressed for the th dimension as follows:where is the inertial weight at the th iteration, and are the acceleration factors for adjusting pbest and gbest, and are random numbers in , is the integer operation function, the value of is 3 , is a constant, and is the standard normal distribution function. The steps of the DPSO algorithm are given as follows.
Step 1. Initialize the parameters of DPSO.
Step 2. Read the BLIF logical netlist and perform polarity conversion.
Step 4. If , go to Step 3; otherwise, let and go to Step 5.
Step 5. If , where is the size of the particle swarm, go to Step 3; otherwise, go to Step 6.
Step 6. Output the optimal MPRM circuit result.
3.4. Verification Method
To compare the timing optimization of the MPRM combinational logic circuit with that of the DPSO and DC algorithms, a verification method was designed. The verification process is shown in Figure 3. MCNC benchmark circuits were used as the MPRM circuit in the verification process. First, the DPSO algorithm was used for timing optimization of the MCNC benchmark circuit, and an equivalent timing was calculated according to (4). Second, the format of the MCNC benchmark circuit was modified. A DC logic synthesis tool was used to restrict conditions such that the available logic gate types were completely consistent with the MPRM. Timing constraint was executed strictly, and compiling was performed. The number of equivalent logic gates was calculated according to the timing optimization results of the DC logic synthesis and (5). Finally, the timing optimization results of the DC logic synthesis and the DPSO were compared.
The DPSO algorithm was implemented using the C++ language and compiled using the g++ compiler under Linux. The timing of the MCNC benchmark circuit was optimized through the DPSO algorithm. For DC recognition and timing optimization of the MCNC benchmark circuit, the said circuit was transformed into the VHDL format. Each optimization result was tested independently 20 times. The DC process is described in detail as follows.
Step 1. MCNC benchmark circuits in BLIF format are translated into logic circuits in VHDL format.
Step 2. In the DC environment, the logic circuits in VHDL format are constrained for timing optimization and are constrained to generate the logic netlist that contains only two-input AND gates, two-input XOR gates, and inverters.
Step 3. According to the timing optimization results, the startpoint and endpoint of the critical path are reported, the number of logical gates on the critical path is added up, and the value of is calculated with (5) while ignoring the timing delay of wires between logic gates.
Step 4. Repeat Steps – above 20 times for each MCNC benchmark circuit.
4. Result Analysis and Discussion
The DPSO algorithm was used for the timing optimization of 17 MPRM logic circuits. The same combinational logic circuit was operated independently 20 times, and the timing of the optimized combinational logic circuit was calculated according to (4). Then, the DC algorithm was used for timing constraint and for setting the same MCNC benchmark circuits to ensure that the logic gates covered in the netlist after logic synthesis are completely consistent with the logic gates in the MPRM circuits. Timing constraint and optimization were performed using the DC algorithm. The timing of the combinational logic circuits was calculated according to (5). Finally, the optimized timing of the combinational logic circuits obtained by the two algorithms was compared to verify the validity of the DPSO algorithm.
As one of the MCNC benchmark circuits, “alu2” has 10 input ports and six output ports. In accordance with the features of MPRM logic circuits, the available logic gates were restricted and timing optimization was performed using the DC algorithm. The timing report of the critical path is shown in Figure 4. Dotted lines reflect the type of the used logic gates and the available logic gates that were restricted into the AND gate, phase inverter, and the XOR gate. According to (4), the equivalent timing delay of “alu2” is 45 seconds.
The circuit after normal timing optimization by DC without restriction on the available logic gates in alu2 is shown in Figure 5. Dotted lines show the types of the used logic gates. Any logic gate in the standard cell library can be used. According to the netlist after the logic synthesis of alu2 and (5), the equivalent timing delay of alu2 is 170 seconds. A comparison of the results in Figures 4 and 5 revealed that the equivalent timing delay in alu2 increased sharply after the available logic gates were restricted. This trend occurred because, during the timing optimization in DC after the restriction, the logic gates that can be used were restricted into the two-input AND gate, phase inverter, and two-input XOR gate according to the MPRM circuit. Therefore, more logic gates were needed to form the logic gate. Without a restriction on the logic gates, DC will use any logic gate to optimize the circuit according to the needs of the logic circuit, thus generating a logic circuit with a small number of equivalent timing delays.
Here, the value of “I/O” represents the total number of inputs and outputs of the logic circuits, “Circuits” represents the names of MCNC benchmark circuits, and “Avg” represents the average value of equipment timing delay. The same combinational logic circuit was operated independently 20 times, the average timing delays obtained for MCNC benchmark circuits using four intelligent algorithms are listed in Table 2, and the average equivalent timing delay generated by the four algorithms is generally close.
Comparisons between the timing optimization results obtained using the DPSO algorithm and DC are listed in Table 3.
Here, the value of “I/O” represents the total number of inputs and outputs of the logic circuits, “Circuits” represents the names of MCNC benchmark circuits, “startpoint” is the input port name of the critical path, “endpoint” is the output port name of the critical path, “Min” represents the minimum value of equipment timing delay, and “Avg” represents the average value of equipment timing delay. We note from Table 3 that the startpoints and endpoints of all critical paths obtained by DC are equivalent to those obtained by the DPSO algorithm, which demonstrates that the proposed algorithm has the same effect as DC for identifying critical paths.
The consistency of the timing optimization provided by the DC tool is demonstrated by the identical “Min” and “Avg” values obtained for the timing delays of each circuit, indicating that DC obtained equivalent values of for all 20 trials of each logic circuit. However, we note that the DPSO algorithm generally provides slightly different “Min” and “Avg” values of . This finding indicates that both DPSO and DC algorithms have unstable factors for the timing optimization of the MPRM combinational logic circuit.
There are certain differences existing between the two algorithms in “Min” and “Avg” after timing optimization of the MPRM logic circuits. As shown in Figure 6, the average timing delay of the critical path obtained by the DPSO algorithm is less than those obtained by DC for all MCNC benchmark circuits considered. DPSO provides an overall average reduction of 9.7% in the timing delays of critical paths, which sufficiently verifies that the DPSO algorithm has a good timing optimization effect for logic circuits between adjacent flip-flops. This outcome suggests that the intelligence algorithm is better than the DC algorithm in terms of timing optimization of MPRM combinational logic circuits.
To verify that an intelligence algorithm is better than the DC algorithm in the timing optimization of MPRM logic circuits, a novel verification method was proposed in this study. First, the DPSO algorithm was used to optimize the timing of the MPRM logic circuits. The equivalent timing delay after timing optimization was calculated. Second, timing constraints and optimization of the MPRM logic circuit were performed using the DC algorithm, and the equivalent timing delay was calculated according to optimization results. Finally, the optimization results of the MCNC benchmark circuits using the two algorithms were analyzed and compared. The proposed verification method is feasible and effective. In this study, MCNC benchmark circuits were used in the verification experiment. The timing optimization results of the two algorithms were converted into the equivalent timing delay. The suggested verification method can determine which algorithm has a better timing optimization ability directly by comparing the experimental data of the two algorithms.
Conflicts of Interest
The authors declare that they have no conflicts of interest.
The authors would like to gratefully acknowledge the financial support of the National Natural Science Foundation of China (Grant no. 61404030).
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