VLSI Design

The Impact of Statistical Leakage Models on Design Yield Estimation

New Considerations for Spectral Classification of Boolean Switching Functions

Shedding Physical Synthesis Area Bloat

A Cost-Effective 10-Bit D/A Converter for Digital-Input MOEMS Micromirror Actuation

Suitability of Various Low-Power Testing Techniques for IP Core-Based SoC: A Survey

Buffer Planning for IP Placement Using Sliced-LFF

Selected Papers from the Midwest Symposium on Circuits and Systems

An Approach for Implementing State Machines with Online Testability

Simple Exact Algorithm for Transistor Sizing of Low-Power High-Speed Arithmetic Circuits

CORDIC Architectures: A Survey

Run-Length-Based Test Data Compression Techniques: How Far from Entropy and Power Bounds?—A Survey

Reduced Voltage Scaling in Clock Distribution Networks

Nonlinear Circuit Analysis via Perturbation Methods and Hardware Prototyping

Low-Cost Allocator Implementations for Networks-on-Chip Routers

FPGA Implementation of an Amplitude-Modulated Continuous-Wave Ultrasonic Ranger Using Restructured Phase-Locking Scheme

VLSI Design

Table of Contents

Table of Contents

The Impact of Statistical Leakage Models on Design Yield Estimation

New Considerations for Spectral Classification of Boolean Switching Functions

Shedding Physical Synthesis Area Bloat

A Cost-Effective 10-Bit D/A Converter for Digital-Input MOEMS Micromirror Actuation

Suitability of Various Low-Power Testing Techniques for IP Core-Based SoC: A Survey

Buffer Planning for IP Placement Using Sliced-LFF

Selected Papers from the Midwest Symposium on Circuits and Systems

An Approach for Implementing State Machines with Online Testability

Simple Exact Algorithm for Transistor Sizing of Low-Power High-Speed Arithmetic Circuits

CORDIC Architectures: A Survey

Run-Length-Based Test Data Compression Techniques: How Far from Entropy and Power Bounds?—A Survey

Reduced Voltage Scaling in Clock Distribution Networks

Nonlinear Circuit Analysis via Perturbation Methods and Hardware Prototyping

Low-Cost Allocator Implementations for Networks-on-Chip Routers

FPGA Implementation of an Amplitude-Modulated Continuous-Wave Ultrasonic Ranger Using Restructured Phase-Locking Scheme