VLSI Design

A Cache System Design for CMPs with Built-In Coherence Verification

A Low Complexity All-Digital Background Calibration Technique for Time-Interleaved ADCs

Unified and Modular Modeling and Functional Verification Framework of Real-Time Image Signal Processors

New Proposal for MCML Based Three-Input Logic Implementation

Improved Switching Energy Reduction Approach in Low-Power SAR ADC for Bioelectronics

An Efficient Reconfigurable Architecture for Fingerprint Recognition

Self-Healing Many-Core Architecture: Analysis and Evaluation

Implementation, Test Pattern Generation, and Comparative Analysis of Different Adder Circuits

Shared Reed-Muller Decision Diagram Based Thermal-Aware AND-XOR Decomposition of Logic Circuits

A Novel Time Synchronization Method for Dynamic Reconfigurable Bus

Ultra-Low-Voltage Self-Body Biasing Scheme and Its Application to Basic Arithmetic Circuits

The Design of Low Noise Amplifiers in Deep Submicron CMOS Processes: A Convex Optimization Approach

A Modularized Noise Analysis Method with Its Application in Readout Circuit Design

Analysis and Implementation of Kidney Stone Detection by Reaction Diffusion Level Set Segmentation Using Xilinx System Generator on FPGA

Functional Testbench Qualification by Mutation Analysis

VLSI Design

Table of Contents

Table of Contents

A Cache System Design for CMPs with Built-In Coherence Verification

A Low Complexity All-Digital Background Calibration Technique for Time-Interleaved ADCs

Unified and Modular Modeling and Functional Verification Framework of Real-Time Image Signal Processors

New Proposal for MCML Based Three-Input Logic Implementation

Improved Switching Energy Reduction Approach in Low-Power SAR ADC for Bioelectronics

An Efficient Reconfigurable Architecture for Fingerprint Recognition

Self-Healing Many-Core Architecture: Analysis and Evaluation

Implementation, Test Pattern Generation, and Comparative Analysis of Different Adder Circuits

Shared Reed-Muller Decision Diagram Based Thermal-Aware AND-XOR Decomposition of Logic Circuits

A Novel Time Synchronization Method for Dynamic Reconfigurable Bus

Ultra-Low-Voltage Self-Body Biasing Scheme and Its Application to Basic Arithmetic Circuits

The Design of Low Noise Amplifiers in Deep Submicron CMOS Processes: A Convex Optimization Approach

A Modularized Noise Analysis Method with Its Application in Readout Circuit Design

Analysis and Implementation of Kidney Stone Detection by Reaction Diffusion Level Set Segmentation Using Xilinx System Generator on FPGA

Functional Testbench Qualification by Mutation Analysis