VLSI Design

Table of Contents

  • VLSI Design -
  • Special Issue
  • - Volume 13
  • - Article ID 058626

IWCE-7 Committees

John R. Barker | Asen Asenov
  • VLSI Design -
  • Special Issue
  • Volume 14
  • - Article ID 590482

Spectral Transforms Calculation through Decision Diagrams

Radomir S. Stanković | Bogdan J. Falkowski
  • VLSI Design -
  • Special Issue
  • Volume 6
  • - Article ID 038125

Quantum Kinetic Transport under High Electric Fields

Nobuyuki Sano | Akira Yoshii
  • VLSI Design -
  • Special Issue
  • Volume 15
  • - Article ID 204130

Genetic Spot Optimization for Peak Power Estimation in Large VLSI Circuits

Michael S. Hsiao
  • VLSI Design -
  • Special Issue
  • Volume 12
  • - Article ID 092781

Two-dimensional Placement Using Tabu Search

John M. Emmert | Dinesh K. Bhatia
  • VLSI Design -
  • Special Issue
  • - Volume 7
  • - Article ID 069289

Clustering Network Modules with Different Implementations for Delay Minimization

Dimitrios Karayiannis | Spyros Tragoudas
  • VLSI Design -
  • Special Issue
  • Volume 15
  • - Article ID 243674

Energy Efficient Signaling in Deep-submicron Technology

Imed Ben Dhaou | Keshab K. Parhi | Hannu Tenhunen
  • VLSI Design -
  • Special Issue
  • - Volume 2
  • - Article ID 032902

TOPS: A Target-Oriented Partial Scan Design Package Based on Simulated Annealing

C. P. Ravikumar | H. Rasheed
  • VLSI Design -
  • Special Issue
  • - Volume 7
  • - Article ID 089432

Power Analysis of a 32-bit Embedded Microcontroller

Vivek Tiwari | Mike Tien-Chien Lee
  • VLSI Design -
  • Special Issue
  • - Volume 9
  • - Article ID 061087

Dynamic Cancellation: Selecting Time Warp Cancellation Strategies at Runtime

Raghunandan Rajan | Radharamanan Radhakrishnan | Philip A. Wilsey
  • VLSI Design -
  • Special Issue
  • - Volume 3
  • - Article ID 012686

Formulation of Macroscopic Transport Models for Numerical Simulation of Semiconductor Devices

Edwin C. Kan | Zhiping Yu | ... | Umberto Ravaioli
  • VLSI Design -
  • Special Issue
  • Volume 14
  • - Article ID 420210

Design Methodology of a 32-bit Arithmetic Logic Unit with an Adaptive Leaf-cell Based Layout Technique

Kiseon Cho | Minkyu Song
  • VLSI Design -
  • Special Issue
  • - Volume 4
  • - Article ID 025839

A Novel Path Delay Fault Simulator Using Binary Logic

Ananta K. Majhi | James Jacob | Lalit M. Patnaik
  • VLSI Design -
  • Special Issue
  • Volume 1
  • - Article ID 019638

An Optimum Channel Routing Algorithm in the Knock-knee Diagonal Model

Xiaoyu Song
  • VLSI Design -
  • Special Issue
  • - Volume 12
  • - Article ID 082129

An Instruction-Level Power Analysis Model with Data Dependency

Giuseppe Ascia | Vincenzo Catania | ... | Davide Sarta

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