VLSI Design

Low-Power Adiabatic Computing with Improved Quasistatic Energy Recovery Logic

FPGA Fault Tolerant Arithmetic Logic: A Case Study Using Parallel-Prefix Adders

Architecture Exploration Based on GA-PSO Optimization, ANN Modeling, and Static Scheduling

Computational Performance Optimisation for Statistical Analysis of the Effect of Nano-CMOS Variability on Integrated Circuits

Design Example of Useful Memory Latency for Developing a Hazard Preventive Pipeline High-Performance Embedded-Microprocessor

Framework for Simulation of Heterogeneous MpSoC for Design Space Exploration

Ingredients of Adaptability: A Survey of Reconfigurable Processors

Power-Driven Global Routing for Multisupply Voltage Domains

Hardware Acceleration of Beamforming in a UWB Imaging Unit for Breast Cancer Detection

Architecture and Implementation of Fading Compensation for Dynamic Spectrum Access Wireless Communication Systems

Faster and Energy-Efficient Signed Multipliers

Design a Bioamplifier with High CMRR

A Prototype-Based Gate-Level Cycle-Accurate Methodology for SoC Performance Exploration and Estimation

LDPC Decoder with an Adaptive Wordwidth Datapath for Energy and BER Co-Optimization

High-Accuracy Programmable Timing Generator with Wide-Range Tuning Capability

VLSI Design

Table of Contents

Table of Contents

Low-Power Adiabatic Computing with Improved Quasistatic Energy Recovery Logic

FPGA Fault Tolerant Arithmetic Logic: A Case Study Using Parallel-Prefix Adders

Architecture Exploration Based on GA-PSO Optimization, ANN Modeling, and Static Scheduling

Computational Performance Optimisation for Statistical Analysis of the Effect of Nano-CMOS Variability on Integrated Circuits

Design Example of Useful Memory Latency for Developing a Hazard Preventive Pipeline High-Performance Embedded-Microprocessor

Framework for Simulation of Heterogeneous MpSoC for Design Space Exploration

Ingredients of Adaptability: A Survey of Reconfigurable Processors

Power-Driven Global Routing for Multisupply Voltage Domains

Hardware Acceleration of Beamforming in a UWB Imaging Unit for Breast Cancer Detection

Architecture and Implementation of Fading Compensation for Dynamic Spectrum Access Wireless Communication Systems

Faster and Energy-Efficient Signed Multipliers

Design a Bioamplifier with High CMRR

A Prototype-Based Gate-Level Cycle-Accurate Methodology for SoC Performance Exploration and Estimation

LDPC Decoder with an Adaptive Wordwidth Datapath for Energy and BER Co-Optimization

High-Accuracy Programmable Timing Generator with Wide-Range Tuning Capability