VLSI Design

Power Consumption Models for Decimation FIR Filters in Multistandard Receivers

A New Length-Based Algebraic Multigrid Clustering Algorithm

Cognitive Radio RF: Overview and Challenges

Redundant Logic Insertion and Latency Reduction in Self-Timed Adders

Low-Complexity Hierarchical Mode Decision Algorithms Targeting VLSI Architecture Design for the H.264/AVC Video Encoder

Low Cost Design of a Hybrid Architecture of Integer Inverse DCT for H.264, VC-1, AVS, and HEVC

Modeling and Design of a Nano Scale CMOS Inverter for Symmetric Switching Characteristics

A System View on Iterative MIMO Detection: Dynamic Sphere Detection versus Fixed Effort List Detection

Performance Analysis of High Speed Hybrid CMOS Full Adder Circuits for Low Voltage VLSI Design

Enabling Fast ASIP Design Space Exploration: An FPGA-Based Runtime Reconfigurable Prototyper

Communication and Memory Architecture Design of Application-Specific High-End Multiprocessors

Low-Complexity Hardware Interleaver/Deinterleaver for IEEE 802.11a/g/n WLAN

9T Full Adder Design in Subthreshold Region

Adaptivity Support for MPSoCs Based on Process Migration in Polyhedral Process Networks

CAD for Gigascale SoC Design and Verification Solutions

VLSI Design

Table of Contents

Table of Contents

Power Consumption Models for Decimation FIR Filters in Multistandard Receivers

A New Length-Based Algebraic Multigrid Clustering Algorithm

Cognitive Radio RF: Overview and Challenges

Redundant Logic Insertion and Latency Reduction in Self-Timed Adders

Low-Complexity Hierarchical Mode Decision Algorithms Targeting VLSI Architecture Design for the H.264/AVC Video Encoder

Low Cost Design of a Hybrid Architecture of Integer Inverse DCT for H.264, VC-1, AVS, and HEVC

Modeling and Design of a Nano Scale CMOS Inverter for Symmetric Switching Characteristics

A System View on Iterative MIMO Detection: Dynamic Sphere Detection versus Fixed Effort List Detection

Performance Analysis of High Speed Hybrid CMOS Full Adder Circuits for Low Voltage VLSI Design

Enabling Fast ASIP Design Space Exploration: An FPGA-Based Runtime Reconfigurable Prototyper

Communication and Memory Architecture Design of Application-Specific High-End Multiprocessors

Low-Complexity Hardware Interleaver/Deinterleaver for IEEE 802.11a/g/n WLAN

9T Full Adder Design in Subthreshold Region

Adaptivity Support for MPSoCs Based on Process Migration in Polyhedral Process Networks

CAD for Gigascale SoC Design and Verification Solutions