This paper introduces a new design approach that combines stages of logic and physical design. The logic function issynthesized and mapped to a two-dimensional array of logic cells. This array generalizes PLAs, XPLAs and cellular Maitracascades. Each cell can be programmed to a wire, an inverter, or a two-input AND, OR or EXOR gate (with any subset ofinputs negated). The gate can take any output of four neighbor cells and four neighbor buses as its inputs, and sends its resultback to them. This two-dimensional geometrical model is well suited for both fine-grain FPGA realization and sea-of-gatescustom ASIC layout. The comprehensive design method starts from a Boolean function, specified as SOP or ESOP, andproduces a rectangularly shaped structure of (mostly) locally connected cells. Two stages: restricted factorization, andcolumn folding, are discussed in more details to illustrate our general methodology.

Ning  Song

Marek A. Perkowski

Malgorzata  Chrzanowska-Jeske

Andisheh  Sarabi

A New Design Methodology for Two-DimensionalLogic Arrays

We examine the cost in router complexity of adaptivity and virtual lanes in wormhole routers, using f-flat adaptive
routers (based on a generalization of <i>planar-adaptive routing</i>) which include routers with a range of routing
freedom. Our studies show that adaptivity is expensive because it requires additional virtual channels and much
larger crossbar switches for both adaptivity and deadlock prevention. Increases of 50 to 100% in channel utilization
are required to justify additional degrees of routing freedom.Three internal router architectures for virtual lanes are examined and the fully expanded crossbar is found to be
most effective because it gives simplest control and minimal internal blocking. Examining router designs with from
1–16 virtual lanes indicates that 30% improvements in channel utilization are required to justify each additional
virtual lane. These studies combined with published simulation results indicate that only modest numbers of virtual
lanes are likely to be cost effective.

Kazuhiro Aoyama

Andrew A. Chien

The Cost of Adaptivity and Virtual Lanes in a
Wormhole Router

High-performance parallel systems demand a high-performance interconnect so that their component parts canexchange data and synchronise efficiently. The interconnect must be cheap, and must also scale well in bothperformance and cost relative to the system size. In this paper we describe the rationale, architecture and operationof the STC104, the first commercially available, general-purpose interconnect chip. The serial protocols used bythe device are described, followed by an overview of the microarchitecture, The operation of the fundamental blockis outlined, including the response to error conditions. Chip-wide design issues and design methodology are discussed,and finally various aspects of performance are calculated.

Peter W. Thompson

Julian D. Lewis

The STC104 Packet Routing Chip

This paper introduces several new families of decision diagrams for multi-output Boolean functions. The introducedfamilies include several diagrams known from literature (BDDs, FDDs) as subsets. Due to this property, these diagrams canprovide a more compact representation of functions than either of the two decision diagrams. Kronecker Decision Diagrams(KDDs) with negated edges are based on three orthogonal expansions (Shannon, Positive Davio, Negative Davio) and arecreated here for incompletely specified Boolean functions as well. An improved efficient algorithm for the construction ofKDD is presented and applied in a mapping program to ATMEL 6000 fine-grain FPGAs. Four other new families offunctional decision diagrams are also presented: Pseudo KDDs, Free KDDs, Boolean Ternary DDs, and Boolean KroneckerTernary DDs. The last two families introduce nodes with three edges and require AND, OR and EXOR gates for circuitrealization. There are two variants of each of the last two families: canonical and non-canonical. While the canonicaldiagrams can be used as efficient general-purpose Boolean function representations, the non-canonical variants are alsoapplicable to incompletely specified functions and create don&#39;t cares in the process of the creation of the diagram.. They leadto even more compact circuits in logic synthesis and technology mapping.

Andisheh   Sarabi

Ingo  Sch&#228;fer

Multi-Level Logic Synthesis Based on KroneckerDecision Diagrams and Boolean Ternary DecisionDiagrams for Incompletely Specified Functions

We present the design for the two VLSI components used in a processor-to-memory interconnection network fora shared memory system. These components allow the combining of requests that are destined to the same memorylocation. The design contains both semi-systolic queues and an associative &#8220;wait buffer.&#8221; Transition equations andschematics of the critical pieces of the design are included.

Susan R. Dickey

Richard  Kenner

Design of Components for a Low Cost CombiningSwitch

An effective logic synthesis procedure based on parallel and serial decomposition of a Boolean function is presented in thispaper. The decomposition, carried out as the very first step of the .synthesis process, is based on an original representationof the function by a set of r-partitions over the set of minterms. Two different decomposition strategies, namely serial andparallel, are exploited by striking a balance between the two ideas. The presented procedure can be applied to completelyor incompletely specified, single- or multiple-output functions and is suitable for different types of FPGAs includingXILINX, ACTEL and ALGOTRONIX devices. The results of the benchmark experiments presented in the paper show that,in several cases, our method produces circuits of significantly reduced complexity compared to the solutions reported in the literature.

Tadeusz  &#321;uba

Henry   Selvaraj

A General Approach to Boolean FunctionDecomposition and its Application in FPGABasedSynthesis

Pradip K. Srimani

Guest Editor&#39;s Introduction

During the last decade, many different approaches have been proposed to solve the multiple-level synthesis problem withdifferent minimum functionally complete systems of primitive logic blocks. The most popular of them is the division-basedapproach. However, modem microelectronic technology provides a large variety of building blocks which considerablydiffer from those typically considered. The traditional methods are therefore not suitable for synthesis with many modembuilding blocks. Furthermore, they often fail to find global optima for complex designs and leave unconsidered someimportant design aspects. Some of their weaknesses can be eliminated without leaving the paradigm they are based on, otherones are more fundamental. A paradigm which enables efficient exploitation of the opportunities created by themicroelectronic technology is the general decomposition paradigm. The aim of this paper is to analyze and compare thegeneral decomposition approach and the division-based approach. The most important advantages of the generaldecomposition approach are its generality (any network of any building blocks can be considered) and totality (all importantdesign aspects can be considered) as well as handling the incompletely specified functions in a natural way. In many cases,the general decomposition approach gives much better results than the traditional approaches.

Frank   Volf

Lech  J&#243;&#378;wiak

Mario  Stevens

Division-Based Versus General Decomposition-Based Multiple-Level Logic Synthesis

Here we present a new method for the decomposition of a Finite State Machine (FSM) into a network of interacting FSMsand a framework for the functional verification of the FSM network at different levels of abstraction. The problem ofdecomposition is solved by output partitioning and state space decomposition using a multiway graph partitioningtechnique. The number of submachines is determined dynamically during the partitioning process. The verificationalgorithm can be used to verify (a) the result of FSM decomposition on a behavioral level, (b) the encoded FSM network,and (c) the FSM network after logic optimization. Our verification technique is based on an efficient enumeration-simulationmethod which involves traversal of the state transition graph of the prototype machine and simulation of the decomposedmachine network. Both the decomposition and verification/simulation algorithms have been implemented as part of aninteractive FSM synthesis system and tested on a set of benchmark examples.

Zafar   Hasan

Maciej J. Ciesielski

FSM Decomposition and Functional Verification ofFSM Networks

Modem microelectronic technology.gives opportunities to build digital circuits of huge complexity and provides a widediversity of logic building blocks. Although logic designers have been building circuits for many years, they have realizedthat advances in microelectronic technology are outstripping their abilities to make use of the created opportunities. In thispaper, we present the fundamentals of a logic design methodology which meets the requirements of today&#39;s complex circuitsand modem building blocks. The methodology is based on the theory of general full-decompositions which constitutes thetheory of digital circuit structures at the highest abstraction level. The paper explains the theory and shows how it can beused for digital circuit synthesis. The decomposition methodology that is presented ensures &#8220;correctness by construction&#8221;and enables very effective and efficient post-factum validation. It makes possible extensive examination of the structuralfeatures of the required information processing in relation to a given set of objectives and constraints.

General Decomposition and Its Use in Digital Circuit Synthesis

To find a minimal expression of a boolean function includes a step to select the minimum cost cover from a set ofimplicants. Since the selection process is an NP-complete problem, to find an optimal solution is impractical forlarge input data size. Neural network approach is used to solve this problem. We first formalize the problem, andthen define an &#8220;energy function&#8221; and map it to a modified Hopfield network, which will automatically search forthe minima. Simulation of simple examples shows the proposed neural network can obtain good solutions most ofthe time.

Pong P. Chu

Applying Neural Networks to Findthe Minimum Cost Coverageof a Boolean Function

According to different assumptions in deriving carrier and energy flux equations, macroscopic semiconductor
transport models from the moments of the Boltzmann transport equation (BTE) can be divided into two main
categories: the hydrodynamic (HD) model which basically follows Bløtekjer's approach [1, 2], and the Energy
Transport (ET) model which originates from Strattton's approximation [3, 4]. The formulation, discretization,
parametrization and numerical properties of the HD and ET models are carefully examined and compared. The
well-known spurious velocity spike of the HD model in simple <i>nin</i> structures can then be understood from its
formulation and parametrization of the thermoelectric current components. Recent progress in treating negative
differential resistances with the ET model and extending the model to thermoelectric simulation is summarized.
Finally, we propose a new model denoted by DUET (Dual ET)which accounts for all thermoelectric effects in
most modern devices and demonstrates very good numerical properties. The new advances in applicability and
computational efficiency of the ET model, as well as its easy implementation by modifying the conventional
drift-diffusion (DD) model, indicate its attractiveness for numerical simulation of advanced semiconductor
devices

Edwin C. Kan

Zhiping Yu

Robert W. Dutton

Datong Chen

Umberto Ravaioli

Formulation of Macroscopic Transport
Models for Numerical Simulation
of Semiconductor Devices

The phenomenon of resonant tunneling is simulated and analyzed in the quantum hydrodynamic (QHD) modelfor semiconductor devices. Simulations of a parabolic well resonant tunneling diode at 77 K are presented whichshow multiple regions of negative differential resistance (NDR) in the current-voltage curve. These are the firstsimulations of the QHD equations to show multiple regions of NDR.Resonant tunneling (and NDR) depend on the quantum interference of electron wavefunctions and thereforeon the phases of the wavefunctions. An analysis of the QHD equations using a moment expansion of theWigner-Boltzmann equation indicates how phase information is retained in the hydrodynamic equations.

Carl L. Gardner

Resonant Tunneling in the QuantumHydrodynamic Model

Transport in one- and two-dimensional semiconductor device structures is considered using a set of quantumcorrected hydrodynamic equations. Simple one-dimensional simulations demonstrate the need to include quantumeffects in structures with sharp interfaces. Application to a two-dimensional quantum well HEMT structure isthen considered. A brief discussion of the computational procedure is also presented.

J.  P. Kreskovsky

H. L. Grubin

Electron Transport Using the QuantumCorrected Hydrodynamic Equations

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VLSI Design

Table of Contents

Table of Contents: 1995

A New Design Methodology for Two-Dimensional Logic Arrays

The Cost of Adaptivity and Virtual Lanes in a Wormhole Router

The STC104 Packet Routing Chip

Multi-Level Logic Synthesis Based on Kronecker Decision Diagrams and Boolean Ternary Decision Diagrams for Incompletely Specified Functions

Design of Components for a Low Cost Combining Switch

A General Approach to Boolean Function Decomposition and its Application in FPGABased Synthesis

Guest Editor's Introduction

Division-Based Versus General Decomposition- Based Multiple-Level Logic Synthesis

FSM Decomposition and Functional Verification of FSM Networks

General Decomposition and Its Use in Digital Circuit Synthesis

Guest Editor's Introduction

Applying Neural Networks to Find the Minimum Cost Coverage of a Boolean Function

Formulation of Macroscopic Transport Models for Numerical Simulation of Semiconductor Devices

Resonant Tunneling in the Quantum Hydrodynamic Model

Electron Transport Using the Quantum Corrected Hydrodynamic Equations