VLSI Design

Table of Contents: 1997

  • VLSI Design -
  • Special Issue
  • - Volume 5
  • - Article ID 059329

VLSI Testing for High Reliability: Mixing IDDQ Testing With Logic Testing

S. Hwang | R. Rajsuman
  • VLSI Design -
  • Special Issue
  • - Volume 5
  • - Article ID 054757

Operational and Test Performance in the Presence of Built-in Current Sensors

Sankaran M. Menon | Yashwant K. Malaiya | ... | Carol Q. Tong
  • VLSI Design -
  • Special Issue
  • - Volume 5
  • - Article ID 097381

Current Testing of CMOS Combinational Circuits with Single Floating Gate Defects

Victor H. Champac | Joan Figueras
  • VLSI Design -
  • Special Issue
  • - Volume 5
  • - Article ID 051094

IDDQ Testing Experiments for Various CMOS Logic Design Structures

A. Toukmaji | R. Helms | ... | R. Toole
  • VLSI Design -
  • Special Issue
  • - Volume 5
  • - Article ID 093809

IDDQ Detectable Bridges in Combinational CMOS Circuits

E. Isern | J. Figueras
  • VLSI Design -
  • Special Issue
  • - Volume 5
  • - Article ID 047423

Application of Dynamic Supply Current Monitoring to Testing Mixed-Signal Circuits

Mahmoud A. Al-Qutayri | Peter R. Shepherd
  • VLSI Design -
  • Special Issue
  • - Volume 5
  • - Article ID 090247
  • - Guest Editorial

Advancements in Power Supply Current Testing

Rafic Z. Makki
  • VLSI Design -
  • Special Issue
  • - Volume 5
  • - Article ID 042849

Layout Modeling and Design Space Exploration in Pss1 System

Fur-Shing Tsai | Yu-Chin Hsu
  • VLSI Design -
  • Special Issue
  • - Volume 5
  • - Article ID 085473

Datapath Optimization Using Layout Information: An Empirical Study

Allen C.-H. Wu
  • VLSI Design -
  • Special Issue
  • - Volume 5
  • - Article ID 039186

Taking Thermal Considerations Into Account During High-Level Synthesis

Jen-Pin Weng | Alice C. Parker
  • VLSI Design -
  • Special Issue
  • - Volume 5
  • - Article ID 081902

Module Selection in Microarchitectural Synthesis for Multiple Critical Constraint Satisfaction

Ian G. Harris | Alex Orailoglu
  • VLSI Design -
  • Special Issue
  • - Volume 5
  • - Article ID 035614

RT Component Sets for High-Level Design Applications

Nikil D. Dutt | Pradip K. Jha
  • VLSI Design -
  • Special Issue
  • - Volume 5
  • - Article ID 078238

Statistical Module Level Area and Delay Estimation

Akhilesh Tyagi
  • VLSI Design -
  • Special Issue
  • - Volume 5
  • - Article ID 030941

Effective Coupling Between Logic Synthesis and Layout Tools for Synthesis of Area and Speed-Efficient Circuits

Mandalagiri S. Chandrasekhar | Robert H. McCharles | David E. Wallace
  • VLSI Design -
  • Special Issue
  • - Volume 5
  • - Article ID 073654

Combining Technology Mapping With Layout

Massoud Pedram | Narasimha Bhat | Ernest S. Kuh

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