A linear (given potential) steady-state Wigner equation is considered in conjunction
with inflow boundary conditions and relaxation-time terms. A brief review of the use of
inflow conditions in the classical case is also discussed. An analytic expansion of
solutions is shown and a recursion relation derived for the given problem under certain
regularity assumptions on the given inflow data. The uniqueness of the physical current
of the solutions is shown and a brief discussion of the lack of charge conservation
associated with the relaxation-time is given.

Horst Lange

Bruce Toomire

P. F. Zweifel

Inflow Boundary Conditions in Quantum Transport Theory

Recent experiments on the formation of crystalline CO2 from a newly discovered binary
phase consisting of CO2 and C2H2 at 90° K fail to be adequately simulated by Avrami
equations. The purpose of this note is to develop an alternative to the Avrami model
which can make accurate predictions for these experiments. The new model uses empirical
approximations to the distribution densities of the volumes of three-dimensional
Voronoi cells defined by Poisson-generated crystallization kernels (nuclei). Inside each
Voronoi cell, the growth of the crystal is assumed to be linear in diameter (i.e., cubic in
volume) until the cell is filled by the CO2 crystals and the C2H2 (thought of as a waste
product). The cumulative growth curve is computed by averaging these individual growth
curves with respect to the distribution density of the volumes of the Voronoi cells. Agreement
with the experiments is excellent.

Terry Gough

Reinhard Illner

Modeling Crystallization Dynamics when the Avrami Model Fails

The reconfigurable mesh (RN-MESH) can solve a large class of problems in constanttime, including problems that require logarithmic time by other, even shared memory,models such as the PRAM with a similar number of processors [3]. In this work we showthat for the RN-MESH these constants can always be reduced to one, still using apolynomial number of processors. Given a reconfigurable mesh that computes a set ofvalues in constant time, we show that it can be simulated by a single step reconfigurablemesh with maximum size that is polynomial in the size of the original mesh. The proof isconstructive, where the construction of the single step RN-MESH holds for therelatively weak undirected RN-MESH model. In this model broadcasts made on busesarrive at all nodes that belong to the undirected connected component of thetransmitting processor. A result similar to the one that is obtained in this work waspreviously obtained for the directed reconfigurable mesh model (DRN) [5]. However,the construction for the DRN-MESH relies on the fact that the buses are directed, andthus cannot be applied to the undirected case. In addition, the construction presentedhere is simpler and uses significantly fewer processors than the one obtained for theDRN-MESH.

Yosi  Ben-Asher

Assaf  Schuster

Single Step Undirected Reconfigurable Networks

Interconnect tuning is an increasingly critical degree of freedom in the physical design ofhigh-performance VLSI systems. By interconnect tuning, we refer to the selection of linethicknesses, widths and spacings in multi-layer interconnect to simultaneously optimizesignal distribution, signal performance, signal integrity, and interconnect manufacturabilityand reliability. This is a key activity in most leading-edge design projects, but hasreceived little attention in the literature. Our work provides the first technology-specificstudies of interconnect tuning in the literature. We center on global wiring layers andinterconnect tuning issues related to bus routing, repeater insertion, and choice ofshielding/spacing rules for signal integrity and performance. We address four basicquestions. (1) How should width and spacing be allocated to maximize performance fora given line pitch&#63; (2) For a given line pitch, what criteria affect the optimal interval atwhich repeaters Should be inserted into global interconnects&#63; (3) Under what circumstancesare shield wires the optimum technique for improving interconnect performance&#63;(4) In global interconnect with repeaters, what other interconnect tuning is possible&#63;Our study of question (4) demonstrates a new approach of offsetting repeater placementsthat can reduce worst-case cross-chip delays by over 30&#37; in current technologies.

Andrew B. Kahng

Sudhakar  Muddu

Egino  Sarto

Tuning Strategies for Global Interconnectsin High-Performance Deep-Submicron ICs

We investigate regularizing dispersive effects for various classical equations, e.g., the
Schrödinger and Dirac equations. After Wigner transform, these dispersive estimates are
reduced to moment lemmas for kinetic equations. They yield new regularization results for
the Schrödinger equation (valid up to the semiclassical limit) and the Dirac equation.

I. Gasser

P. A. Markowich

B. Perthame

Dispersion Lemmas Revisited

We show an existence and uniqueness result for mildly nonlinear Schrödinger systems of
(self-consistent) Hartree–Fock form. We also shortly resume the already existing results
on the semiclassical limit and the asymptotic and dispersive behavior of such systems.

On Hartree–Fock Systems

The “smooth” quantum hydrodynamic (QHD) model is derived specifically to handle
in a mathematically rigorous way the discontinuities in the classical potential energy
which occur at heterojunction barriers in quantum semiconductor devices. Smooth QHD
model simulations of the resonant tunneling diode are presented which exhibit enhanced
negative differential resistance when compared with simulations using the original O(ħ2)
QHD model. In addition, smooth QHD simulations of a classical electron shock wave are
presented which agree with classical hydrodynamic model simulations and which do not
exhibit the spurious dispersive oscillations of the O(ħ2) QHD model.

Carl L. Gardner

Theory and Simulation of the Smooth Quantum
Hydrodynamic Model

We consider the motion of a single electron under phonon scattering caused by a crystal
lattice. Starting from the Fröhlich Hamiltonian in the second quantization formalism
we derive a kinetic transport model by using the Wigner transformation. Under the
assumption of small electron-phonon interaction we derive asymptotically the operator
representing electron-phonon scattering in the Wigner equation. We then consider some
scaling limits and finally we give the connection of our result to the well known Barker-Ferry equation.

Florian Frommlet

Peter A. Markowich

Christian Ringhofer

A Wignerfunction Approach to Phonon Scattering

Transparent boundary conditions (TBCs) for general Schrödinger-type equations on a
bounded domain can be derived explicitly under the assumption that the given potential
V is constant on the exterior of that domain. In 1D these boundary conditions are non-local
in time (of memory type).Existing discretizations of these TBCs have accuracy problems and render the overall
Crank–Nicolson finite difference method only conditionally stable. In this paper a
novel discrete TBC is derived directly from the discrete whole-space problem that yields
an unconditionally stable scheme. Numerical examples illustrate the superiority of the
discrete TBC over other existing consistent discretizations of the differential TBCs.As an application of these boundary conditions to wave propagation problems in
underwater acoustics results for the so-called standard and wide angle “parabolic”
equation (SPE, WAPE) models are presented.

Matthias Ehrhardt

Discrete Transparent Boundary Conditions for General
Schrödinger-type Equations

In this paper, we perform a mathematical study of a semiconductor superlattice. Since thethickness of the layers is very small, quantization plays an important role. The modellingis therefore given by a Schr&#246;dinger equation with a periodic potential. The scaled latticethickness is denoted by a small parameter &#8455; which is of the same order of magnitude asthe Planck constant. When this parameter tends to zero, i.e., the semi-classical limit, weobtain classical transport of the charge carriers described by a Vlasov equation.

Philippe  Bechouche

Semi-classical Limit in a Semiconductor Superlattice

Guest Editorial

We introduce, in this paper, Clustered Time Warp (CTW), an algorithm for the parallelsimulation of discrete event models on a general purpose distributed memoryarchitecture. CTW has its roots in the problem of distributed logic simulation. It is ahybrid algorithm which makes use of Time Warp between clusters of LPs and asequential algorithm within the clusters whereas Time Warp is traditionallyimplemented between individual LPs.We also develop a family of three checkpointing algorithms for use with CTW, each ofwhich occupies a different point in the spectrum of possible trade-offs between memoryusage and execution time. The algorithms were implemented and tested on several digitallogic circuits and their speed, number of states saved and maximal memory consumptionwere compared to Time Warp. Our results showed that one of the algorithms saved anaverage of 40&#37; of the maximal memory consumed by Time Warp while the other twodecreased the maximal usage by 15 and 22&#37;, respectively. The latter two algorithmsexhibited a speed comparable to Time Warp, while the first algorithm was 60&#37; slower.We investigated the scalability of CTW using 3 different queuing models and differentservice-time distributions and showed that the algorithm acts to limit the explosion ofrollbacks exhibited by Time Warp. Furthermore, we showed that the memoryrequirements for CTW are three times smaller than that of Time Warp for one modeland half as large for the two other models.

Herv&#233;  Avril

Carl  Tropper

Scalable Clustered Time Warp and Logic Simulation

In an optimistic parallel simulation, logical processes (Ips) proceed with their
computation without any constraints. However, if the computing requirements of
different lps are not balanced or if the processors are not homogeneous, some lps may
lag behind in simulation time while others surge forward. In other words, if the
simulation clocks of different lps are not progressing at the same rate, cascading
rollbacks may occur nullifying the potential benefit of an optimistic parallel discrete
event simulation (PDES). Hence it is necessary to balance the computational load on
different lps in such a way that their local simulation clocks advance almost at the same
rate. In this paper, we propose two algorithms for dynamic load balancing which reduce
the number of rollbacks in an optimistic PDES system. Our first algorithm is based on
the load transfer mechanism between lps; while the second algorithm, based on the
principle of evolutionary strategy, migrates logical processes between several pairs of
physical processors. We have implemented both of these algorithms on a cluster of
heterogeneous workstations and studied their performance. The experimental results
show that the algorithm based on the load transfer is effective when the grain size is
greater than 10 milliseconds. The algorithm based on the process migration yields good
performance only for grain sizes of 20 milliseconds or larger. In both of these cases the
speed up ranges mostly between and 2 using four processors.

Falguni Sarkar

Sajal K. Das

Design and Implementation of Dynamic
Load Balancing Algorithms for Rollback Reduction
in Optimistic PDES

A partitioning algorithm for parallel discrete event gate-level logic simulations is
proposed in this paper. Unlike most other partitioning algorithms, the proposed
algorithm preserves computation concurrency by assigning to processors circuit gates
that can be evaluated at about the same time. As a result, the improved concurrency
preserving partitioning (iCPP) algorithm can provide better load balancing throughout
the period of a parallel simulation. This is especially important when the algorithm is
used together with a Time Warp simulation where a high degree of concurrency can lead
to fewer rollbacks and better performance. The algorithm consists of three phases and
three conflicting goals can be separately considered so to reduce computational
complexity.To evaluate the quality of partitioning algorithms in terms of preserving concurrency,
a concurrency metric that requires neither sequential nor parallel simulation is
proposed. A levelization technique is used in computing the metric so to determine
gates which can be evaluated at about the same time. A parallel gate-level logic
simulator is implemented on an INTEL Paragon and an IBM SP2 to evaluate the
performance of the iCPP algorithm. The results are compared with several other
partitioning algorithms to show that the iCPP algorithm does preserve concurrency
pretty well and reasonable speedup may be achieved with the algorithm.

Hong K. Kim

Jack Jean

Concurrency Preserving Partitioning Algorithm for
Parallel Logic Simulation

Important layout properties of electronic circuits include space requirements and
interconnection lengths. In the process of designing these circuits, a reliable pre-layout
interconnection length estimation is essential for improving placement and routing
techniques. Donath found an upper bound for the average interconnection length that
follows the trends of experimentally observed average lengths. Yet, this upper bound
deviates from the experimental value by a factor <mml:math id="E1" xmlns:mml="http://www.w3.org/1998/Math/MathML"><mml:mrow><mml:mi>δ</mml:mi><mml:mtext> </mml:mtext><mml:mo>≈</mml:mo><mml:mtext> </mml:mtext><mml:mn>2</mml:mn></mml:mrow></mml:math>, which is not sufficiently accurate
for some applications. We show that we obtain a significantly more accurate estimate by
taking into account the inherent features of the optimal placement process.

Dirk Stroobandt

Jan  Van Campenhout

Accurate Interconnection Length Estimations for Predictions Early in the Design Cycle

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