In this article we concisely present several modern strategies that are applicable to driftdominated
carrier transport in higher-order deterministic models such as the driftdiffusion,
hydrodynamic, and quantum hydrodynamic systems. The approaches include
extensions of “upwind” and artificial dissipation schemes, generalization of the traditional
Scharfetter – Gummel approach, Petrov – Galerkin and streamline-upwind Petrov
Galerkin (SUPG), “entropy” variables, transformations, least-squares mixed methods
and other stabilized Galerkin schemes such as Galerkin least squares and discontinuous
Galerkin schemes. The treatment is representative rather than an exhaustive
review and several schemes are mentioned only briefly with appropriate reference
to the literature. Some of the methods have been applied to the semiconductor device
problem while others are still in the early stages of development for this class of applications.
We have included numerical examples from our recent research tests with
some of the methods. A second aspect of the work deals with algorithms that employ
unstructured grids in conjunction with adaptive refinement strategies. The full benefits
of such approaches have not yet been developed in this application area and we
emphasize the need for further work on analysis, data structures and software to
support adaptivity. Finally, we briefly consider some aspects of software frameworks.
These include dial-an-operator approaches such as that used in the industrial simulator
PROPHET, and object-oriented software support such as those in the SANDIA
National Laboratory framework SIERRA.

Graham F. Carey

A. L. Pardhanani

S. W. Bova

Advanced Numerical Methods and Software Approaches
for Semiconductor Device Simulation

Inner product calculations are often required in digital neural computing. The criticalpath of the inner product of two binary vectors is the carry propagation delay generatedfrom individual product terms. In this work, two architectures to arrange digital ratioedcompressors are presented to reduce the carry propagation delay in the critical path.Besides, the carry propagation delay estimation of these compressor building blocks isderived and compared. The theoretical analysis and Verilog simulation both indicatethat one of the compressor building blocks we present here might offer a sub-optimalsolution for the basic building blocks used in digital hardware realization of the innerproduct computation.

Chua-Chin  Wang

Chenn-Jung  Huang

Po-Ming  Lee

Design and Analysis of Digital Ratioed Compressors for Inner Product Processing

The first completely physical electro-thermal model is presented that is capable of
describing the large signal performance of MESFET- and HEMT-based, high power
microwave and millimeter wave monolithic and hybrid ICs, on timescales suitable for
CAD. The model includes the effects of self-heating and mutual thermal interaction
on active device performance with full treatment of all thermal non linearities. The
electrical description is provided by the rapid quasi-2D Leeds Physical Model and the
steady-state global thermal description is provided by a highly accurate and computationally
inexpensive analytical thermal resistance matrix approach. The order of
the global thermal resistance matrix describing 3-dimensional heat flow in complex
systems, is shown to be determined purely by the number of active device elements, not
the level of internal device structure. Thermal updates in the necessarily iterative, fully
coupled electro-thermal solution, therefore reduce to small matrix multiplications
implying orders of magnitude speed-up compared to the use of full numerical thermal
solutions capable of comparable levels of detail and accuracy.

W. Batty

A. J. Panks

R. G. Johnson

C. M. Snowden

Electro-thermal Modelling of Monolithic and Hybrid
Microwave and Millimeter Wave IC's

An architecture for a Cell Switch Fabric (CSF) with a new bus assignment strategy ispresented. The proposed architecture has a modular structure with a chip partitioningoriented to avoid the system from falling down totally, thus achieving expandability andincreasing reusability. A discussion about different algorithms for the bus assignmentis given. The shared bus is assigned in a cyclic and rotative way, switching microcellsinstead of cells. The CSF is built in four PCBs where every one has a capacity for fourports at 164.323 Mbps, the external port rate is 155.52 Mbps. A microcontroller realizessome tests and communicates with a PC, which runs a test, verification and CSFconfiguration program. Some parameters about the CSF behavior are measured too.Each Port was implemented on a CPLD FLEX10K100 and the Switch Control Blockon a circuit MAX7128, both from Altera Company.

D.  Torres

J.  Gonzalez

M.  Guzman

A New Bus Assignment Algorithm for a Shared Bus Switch Fabric

A high speed 64b/32b integer divider employing digit-recurrence division method andthe on-the-fly conversion algorithm, wherein a fast normalizer is included, which is usedas the pre-processor of the proposed integer divider. For the sake of enhancingthroughput rate, the proposed divider uses a mixed radix-8/4/2 division instead of thetraditional radix-2 division. On-the-fly remainder adjustment is also realized in theconverter module of the divider. The entire design is written in Verilog HDL (hardwaredescription language) employing COMPASS 0.6 &#956;m 1P3M cell library (V3.0), and thensynthesized by SYNOPSYS. The simulation results indicate that our design is a betteroption than the existing long divider designs.

I-Yen  Chang

Design and Analysis of Radix-8/4/2 64b/32b Integer Divider Using COMPASS Cell Library

Balance equations based on the moment method for the transport of electrons in silicon
semiconductors are presented. The energy band is assumed to be described by the Kane
dispersion relation. The closure relations have been obtained by employing the maximum
entropy principle.The validity of the constitutive equations for fluxes and production terms of the
balance equations has been checked with a comparison to detailed Monte Carlo
simulations in the case of bulk silicon.

A. M. Anile

O. Muscato

V. Romano

Moment Equations with Maximum Entropy Closure
for Carrier Transport in Semiconductor Devices:
Validation in Bulk Silicon

A general framework for designing current-mode CMOS analog multiplier/divider
circuits based on the cascade connection of a geometric-mean circuit and a squarer/divider is presented. It is shown how both building blocks can be readily obtained from
a generic second-order MOS translinear loop. Various implementations are proposed,
featuring simplicity, favorable precision and wide dynamic range. They can be successfully
employed in a wide range of analog VLSI processing tasks. Experimental
results of two versions, based on stacked and folded MOS-translinear loops and fabricated
in a 2.4-μm CMOS process, are provided in order to verify the correctness of
the proposed approach.

Antonio J. Lopez-Martin

Alfonso Carlosena

Design of MOS-translinear Multiplier/Dividers in Analog VLSI

Carl L. Gardner

Guest Editorial

Dynamic reconfigurable field-programmable logic arrays (FPGAs) are receiving notableattention because of their much shorter reconfiguration time as compared withtraditional FPGAs. The short reconfiguration time is vital to applications such asreconfigurable computing and emulation. We show in this paper that testing anddiagnosis of the FPGA also can take advantage of its dynamic reconfigurability. Wefirst propose an efficient methodology for testing the interconnects of the FPGA, thenpresent several universal test and diagnosis approaches which cover all functional unitsof the FPGA. Experimental results show that our approach significantly reduces thetesting time, without additional cost for diagnosis.

Chi-Feng  Wu

Cheng-Wen  Wu

Testing and Diagnosing Dynamic Reconfigurable FPGA

A lookup table based method to minimize Generalized Partially-Mixed-Polarity Reed-Muller (GPMPRM) expansions with k mixed polarity variables has been developed.The new algorithm can produce solutions based on the desired cost criteria for thesystems of completely specified functions.

Bogdan J. Falkowski

Chip-Hong  Chang

Minimization of k-Variable-Mixed-Polarity Reed-Muller Expansions

As the demand for higher performance computers for the processing of remote sensingscience algorithms increases, the need to investigate new computing paradigms isjustified. Field Programmable Gate Arrays enable the implementation of algorithmsat the hardware gate level, leading to orders of magnitude performance increase overmicroprocessor based systems. The automatic classification of spaceborne multispectralimages is an example of a computation intensive application that can benefitfrom implementation on an FPGA-based custom computing machine (adaptive orreconfigurable computer). A probabilistic neural network is used here to classify pixelsof a multispectral LANDSAT-2 image. The implementation described utilizes Javaclient/server application programs to access the adaptive computer from a remote site.Results verify that a remote hardware version of the algorithm (implemented on anadaptive computer) is significantly faster than a local software version of the samealgorithm (implemented on a typical general-purpose computer).

Marco A. Figueiredo

Clay S. Gloster

Mark  Stephens

Corey A. Graves

Mouna   Nakkar

Implementation of Multispectral Image Classificationon a Remote Adaptive Computer

Partitioning is a fundamental problem in the design of VLSI circuits. In recent years, themulti-level partitioning approach has been used with success by a number ofresearchers. This paper describes a new multi-level partitioning algorithm (PART) thatcombines a blend of iterative improvement and clustering, biasing of node gains, andlocal uphill climbs. PART is competitive with recent state-of-the-art partitioningalgorithms. PART was able to find new lower cuts for many benchmark circuits. Undersuitably mild assumptions, PART also runs in linear time.

Youssef  Saab

A New 2-way Multi-level Partitioning Algorithm

In this paper, we present a new multilevel k-way hypergraph partitioning algorithm thatsubstantially outperforms the existing state-of-the-art K-PM/LR algorithm for multi-waypartitioning, both for optimizing local as well as global objectives. Experiments onthe ISPD98 benchmark suite show that the partitionings produced by our scheme are onthe average 15&#37; to 23&#37; better than those produced by the K-PM/LR algorithm, bothin terms of the hyperedge cut as well as the (K &#8211; 1) metric. Furthermore, our algorithmis significantly faster, requiring 4 to 5 times less time than that required by K-PM/LR.

George  Karypis

Vipin  Kumar

Multilevel k-way Hypergraph Partitioning

Several classes of modern applications demand very high performance from systems
with minimal resources. These applications must also be flexible to operate in a rapidly
changing environment. Achieving high performance from limited resources demands
application-specific architectures, while flexibility requires architectural adaptation
capabilities. Reconfigurable computing devices promise to meet both needs. While these
devices are currently available, the issue of how to design these systems is unresolved.
This paper describes an environment for design capture, analysis and synthesis of
dynamically adaptive computing applications. The representation methodology is captured
in a Domain-Specific, Model-Integrated Computing framework. Formal analysis
tools are integrated into the design flow to analyze the design space to produce a
constrained set of solutions. HW/SW Co-simulations verify the function of the system
prior to implementation. Finally, a set of hardware and software subsystems are
synthesized to implement the multi-modal, dynamically adaptive application. The application
executes under a runtime environment, which supports common execution
semantics across software and hardware. An application example is presented.

Ted Bapty

Sandeep Neema

Jason Scott

Janos Sztipanovits

Sameh Asaad

Model-integrated Tools for the Design of Dynamically
Reconfigurable Systems

The main goal of the paper is to explore the effectiveness of a new method called TabuSearch &#91;1&#93; on partitioning and compare it with two techniques widely used in CAD toolsfor circuit partitioning i.e., Sanchis Interchange method and Simulated Annealing, interms of the running time and quality of solution. The proposed method integrates thewell known iterative multi-way interchange method with Tabu Search and leads to avery powerful network partitioning heuristic. It is characterized by an ability to escapelocal optima which usually cause simple descent algorithms to terminate by using ashort term memory of recent solutions. Moreover, Tabu Search permits backtracking toprevious solutions, which explore different directions and generates better partitions.The quality of the test results on MCNC benchmark circuits are very promising inmost cases. Tabu Search yields netlist partitions that contain 20&#37;&#8211;67&#37; fewer cut netsand are generated 2/3 to (1/2) times faster than the best netlist partitions obtained byusing an interchange method. Comparable partitions to those obtained by SimulatedAnnealing are obtained 5 to 20 times faster.

Shawki  Areibi

Anthony  Vannelli

Tabu Search: A Meta Heuristic for Netlist Partitioning

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VLSI Design