Frequently, the logic designer deals with functions with symbolic input variables. The binary encoding of such symbols should be chosen to optimize the final implementation. Conventionally, this input encoding (IE) problem has been solved in a two-step process. First step generates constraints on the relationship between codes for different symbols, called group constraints. In a following step, symbols are encoded such that constraints are satisfied. This paper addresses the partial input encoding problem (PIE), a variation of the IE problem which generates codes of minimum length. The role of group constraints within the framework of the PIE problem has been questioned. This paper describes an algorithm that unlike conventional approaches, which try to maximize the number of satisfied constraints, targets the economical implementation of each input constraint. The proposed approach is based on a powerful heuristic that produces high quality results in shorter time compared to previous algorithm.

Manuel  Mart&#237;nez

Mar&#237;a J. Avedillo

Jos&#233; M. Quintana

Jos&#233; L. Huertas

COPAS: A New Algorithm for the Partial Input Encoding Problem

This paper presents a synthesizable VHDL model of a three-dimensional hyperbolic positioning system algorithm. The algorithm obtains an exact solution for the three-dimensional location of a mobile given the locations of four fixed stations (like a global positioning system [GPS] satellite or a base station in a cell) and the signal time of arrival (TOA) from the mobile to each station. The detailed derivation of the steps required in the algorithm is presented. A VHDL model of the algorithm was implemented and simulated using the IEEE numeric&#95;std package. Signals were described by a 32-bit vector. Simulation results predict location of the mobile is off by 1 m for best case and off by 36 m for worst case. A C &#43; &#43; program using real numbers was used as a benchmark for the accuracy and precision of the VHDL model. The model can be easily synthesized for low power hardware implementation.

Ralph  Bucher

D.  Misra

A Synthesizable VHDL Model of the Exact Solution for Three-dimensional Hyperbolic Positioning System

Synthesis for testability ensures that the synthesized circuit is testable by exploring the fundamental relationship between don't care and redundancy. With the exploration of the relationship, redundancy removal can be applied to improve the testability, reduce the area and improve the speed of a synthesized circuit. The test generation problems have been adequately solved, therefore an innovative testability synthesis strategy is necessary for achieving the maximum fault coverage and area reduction for maximum speed. This paper presents a testability synthesis methodology applicable to a top–down design method based on the identification and removal of redundant faults. Emphasis has been placed on the testability synthesis of a high-speed binary jumping carry adder. A synthesized 32-bit testable adder implemented by a 1.2 μm CMOS technology performs addition in 4.09 ns. Comparing with the original synthesized circuit, redundancy removal yields a 100% testable design with a 15% improvement in speed and a 25% reduction in area.

Chien-In Henry Chen

Mahesh Wagh

Testability Synthesis for Jumping Carry Adders

This paper presents two primary results relevant to physical design problems in CAD/VLSI through a case study of the linear placement problem. First a local search mechanism which incorporates a sophisticated neighborhood operator based on constraint relaxation is proposed. The strategy exhibits many of the desirable features of analytical placement while retaining the flexibility and non-determinism of local search. The second and orthogonal contribution is in netlist clustering. We characterize local optima in the linear placement problem through a simple visualization tool&#8212;the displacement graph. This characterization reveals the relationship between clusters and local optima and motivates a dynamic clustering scheme designed specifically for escaping such local optima. Promising experimental results are reported.

Sung-Woo  Hur

John  Lillis

Relaxation and Clustering in a Local Search Framework: Application to Linear Placement

In this note, optimal hardware architectures for the orthogonal and biorthogonal wavelet transforms are presented. The approach used here is not the standard lifting method, but takes advantage of the symmetries inherent in the coefficients of the transforms and the decimation/interpolation operators. The design is based on a highly optimized datapath, which seamlessly integrates both orthogonal and biorthogonal transforms, data extension at the edges and the forward and inverse transforms. The datapath design could be further optimized for speed or low power. The datapath is controlled by a small fast control unit which is hard programmed according to the wavelet or wavelets required by the application. Example circuits are given, including one for the Daubechies 9-7 wavelet which requires only 2.5 multipliers for each input data value, when the equivalent for lifting is 3.

G.  Knowles

Hardware Architectures for the Orthogonal and Biorthogonal Wavelet Transform

With the advent of VLSI technology, circuits with more than one million transistors have been integrated onto a single chip. As the complexity of ICs grows, the time and money spent on designing the circuits become more important. A large, often dominant, part of the cost and time required to design an IC is consumed in the routing operation. The routing of carriers, such as in IC chips and printed circuit boards, is a classical problem in Computer Aided Design. With the complexity inherent in VLSI circuits, high performance routers are necessary. In this paper, a crucial step in the channel routing technique, the single row routing (SRR) problem, is considered. First, we discuss the relevance of SRR in the context of the general routing problem. Secondly, we show that heuristic algorithms are far from solving the general problem. Next, we introduce evolutionary computation, and, in particular, genetic algorithms (GAs) as a justifiable method in solving the SRR problem. Finally, an efficient O (nk) complexity technique based on GAs heuristic is obtained to solve the general SRR problem containing n nodes. Experimental results show that the algorithm is faster and can often generate better results than many of the leading heuristics proposed in the literature.

Albert Y. Zomaya

Roger Karpin

Stephan Olariu

The Single Row Routing Problem Revisited: A Solution Based on Genetic Algorithms

A digital circuit includes two main parts: a controller and a datapath. After connection of these two parts, both are subject to a sharp fall in testability due to the lack of controllability and observability at the interface. In this paper, we propose a method for specifying the control part in order to restore the testability of the datapath to a level close to the initial one, in other words its testability before connection. This testability driven specification affects the next state logic as well as the decoder part of the controller but does not make use of any scan-based element. Based on the finite automata theory and on results of a testability analysis performed on the datapath, the proposed method entails very little area penalty.

M. L. Flottes

B.  Rouzeyre

L.  Volpe

Improving Datapath Testability by Modifying Controller Specification

Bogdan J. Falkowski

Spectral Techniques and Decision Diagrams&#8212;Guest Editorial

In this paper, we present a novel fault detection and fault diagnosis technique for Field Programmable Gate Arrays (FPGAs). The cell is configured to implement a bijective function to simplify the testing of the whole cell array. The whole chip is partitioned into disjoint one-dimensional arrays of cells. For the lookup table (LUT), a fault may occur at the memory matrix, decoder, input or output lines. The input patterns can be easily generated with a k-bit binary counter, where k denotes the number of input lines of a configurable logic block (CLB). Theoretical proofs show that the resulting fault coverage is 100%. According to the characteristics of the bijective cell function, a novel built-in self-test structure is also proposed. Our BIST approaches have the advantages of requiring less hardware resources for test pattern generation and output response analysis. To locate a faulty CLB, two diagnosis sessions are required. However, the maximum number of configurations is k + 4 for diagnosing a faulty CLB. The diagnosis complexity of our approach is also analyzed. Our results show that the time complexity is independent of the array size of the FPGA. In other words, we can make the FPGA array C-diagnosable.

Shyue-Kung Lu

Fu-Min Yeh

Jen-Sheng Shih

Fault Detection and Fault Diagnosis Techniques for Lookup Table FPGAs

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