VLSI Design

A Graph-Based Approach to Optimal Scan Chain Stitching Using RTL Design Descriptions

Absolute Difference and Low-Power Bus Encoding Method for LCD Digital Display Interfaces

A ±6 ms-Accuracy, 0.68 mm², and 2.21 μW QRS Detection ASIC

A Novel Framework for Applying Multiobjective GA and PSO Based Approaches for Simultaneous Area, Delay, and Power Optimization in High Level Synthesis of Datapaths

Line Search-Based Inverse Lithography Technique for Mask Design

Digital Noise Generator Design Using Inverted 1D Tent Chaotic Map

Design of an All-Digital Synchronized Frequency Multiplier Based on a Dual-Loop (D/FLL) Architecture

VLSI Circuits, Systems, and Architectures for Advanced Image and Video Compression Standards

Flexible Radio Design: Trends and Challenges in Digital Baseband Implementation

Design Space Exploration of Deeply Nested Loop 2D Filtering and 6 Level FSBM Algorithm Mapped onto Systolic Array

Automatic Generation of Optimized and Synthesizable Hardware Implementation from High-Level Dataflow Programs

Homogeneous and Heterogeneous MPSoC Architectures with Network-On-Chip Connectivity for Low-Power and Real-Time Multimedia Signal Processing

FastRoute: An Efficient and High-Quality Global Router

Point DCT VLSI Architecture for Emerging HEVC Standard

A Systematic Methodology for Reliability Improvements on SoC-Based Software Defined Radio Systems

VLSI Design

Table of Contents

Table of Contents: 2012

A Graph-Based Approach to Optimal Scan Chain Stitching Using RTL Design Descriptions

Absolute Difference and Low-Power Bus Encoding Method for LCD Digital Display Interfaces

A ±6 ms-Accuracy, 0.68 mm², and 2.21 μW QRS Detection ASIC

A Novel Framework for Applying Multiobjective GA and PSO Based Approaches for Simultaneous Area, Delay, and Power Optimization in High Level Synthesis of Datapaths

Line Search-Based Inverse Lithography Technique for Mask Design

Digital Noise Generator Design Using Inverted 1D Tent Chaotic Map

Design of an All-Digital Synchronized Frequency Multiplier Based on a Dual-Loop (D/FLL) Architecture

VLSI Circuits, Systems, and Architectures for Advanced Image and Video Compression Standards

Flexible Radio Design: Trends and Challenges in Digital Baseband Implementation

Design Space Exploration of Deeply Nested Loop 2D Filtering and 6 Level FSBM Algorithm Mapped onto Systolic Array

Automatic Generation of Optimized and Synthesizable Hardware Implementation from High-Level Dataflow Programs

Homogeneous and Heterogeneous MPSoC Architectures with Network-On-Chip Connectivity for Low-Power and Real-Time Multimedia Signal Processing

FastRoute: An Efficient and High-Quality Global Router

Point DCT VLSI Architecture for Emerging HEVC Standard

A Systematic Methodology for Reliability Improvements on SoC-Based Software Defined Radio Systems

VLSI Design

Table of Contents

Table of Contents: 2012

A Graph-Based Approach to Optimal Scan Chain Stitching Using RTL Design Descriptions

Absolute Difference and Low-Power Bus Encoding Method for LCD Digital Display Interfaces

A ±6 ms-Accuracy, 0.68 mm2, and 2.21 μW QRS Detection ASIC

A Novel Framework for Applying Multiobjective GA and PSO Based Approaches for Simultaneous Area, Delay, and Power Optimization in High Level Synthesis of Datapaths

Line Search-Based Inverse Lithography Technique for Mask Design

Digital Noise Generator Design Using Inverted 1D Tent Chaotic Map

Design of an All-Digital Synchronized Frequency Multiplier Based on a Dual-Loop (D/FLL) Architecture

VLSI Circuits, Systems, and Architectures for Advanced Image and Video Compression Standards

Flexible Radio Design: Trends and Challenges in Digital Baseband Implementation

Design Space Exploration of Deeply Nested Loop 2D Filtering and 6 Level FSBM Algorithm Mapped onto Systolic Array

Automatic Generation of Optimized and Synthesizable Hardware Implementation from High-Level Dataflow Programs

Homogeneous and Heterogeneous MPSoC Architectures with Network-On-Chip Connectivity for Low-Power and Real-Time Multimedia Signal Processing

FastRoute: An Efficient and High-Quality Global Router

Point DCT VLSI Architecture for Emerging HEVC Standard

A Systematic Methodology for Reliability Improvements on SoC-Based Software Defined Radio Systems

A ±6 ms-Accuracy, 0.68 mm², and 2.21 μW QRS Detection ASIC