3D integration can greatly benefit future many-cores by enabling low-latency three-dimensional Network-on-Chip (3D-NoC) topologies. However, due to high cost, low yield, and frequent failures of Through-Silicon Via (TSV), 3D-NoCs are most likely to include only a few vertical connections, resulting in incomplete topologies that pose new challenges in terms of deadlock-free routing and TSV assignment. The routers of such networks require a way to locate the nodes that have vertical connections, commonly known as elevators, and select one of them in order to be able to reach other layers when necessary. In this paper, several alternative TSV selection strategies requiring a constant amount of configurable bits per router are introduced. Each proposed solution consists of a configuration algorithm, which provides each router with the necessary information to locate the elevators, and a routing algorithm, which uses this information at runtime to route packets to an elevator. Our algorithms are compared by simulation to highlight the advantages and disadvantages of each solution under various scenarios, and hardware synthesis results demonstrate the scalability of the proposed approach and its suitability for cost-oriented designs.

Amir Charif

Alexandre Coelho

Nacer-Eddine Zergainoh

Michael Nicolaidis

A Framework for Scalable TSV Assignment and Selection in Three-Dimensional Networks-on-Chips

Multilevel Cell Spin-Transfer Torque Random Access Memory (MLC STT-RAM) is a promising nonvolatile memory technology to build registers for its natural immunity to electromagnetic radiation in rad-hard space environment. Unlike traditional SRAM-based registers, MLC STT-RAM exhibits unbalanced write state transitions due to the fact that the magnetization directions of hard and soft domains cannot be flipped independently. This feature leads to nonuniform costs of write states in terms of latency and energy. However, current SRAM-targeting register allocations do not have a clear understanding of the impact of the different write state-transition costs. As a result, those approaches heuristically select variables to be spilled without considering the spilling priority imposed by MLC STT-RAM. Aiming to address this limitation, this paper proposes a state-transition-aware spilling cost minimization (SSCM) policy, to save power when MLC STT-RAM is employed in register design. Specifically, the spilling cost model is first constructed according to the linear combination of different state-transition frequencies. Directed by the proposed cost model, the compiler picks up spilling candidates to achieve lower power and higher performance. Experimental results show that the proposed SSCM technique can save energy by 19.4&#x25; and improve the lifetime by 23.2&#x25; of MLC STT-RAM-based register design.

Yuanhui Ni

Zhiyao Gong

Weiwen Chen

Chengmo Yang

Keni Qiu

State-Transition-Aware Spilling Heuristic for MLC STT-RAM-Based Registers

Ting-Li Chu

Sin-Hong Yu

Chorng-Sii Hwang

Corrigendum to &#x201c;High-Accuracy Programmable Timing Generator with Wide-Range Tuning Capability&#x201d;

This paper proposes a novel bus encoding method on MBUS in order to reduce the power consumption of system-on-chips (SoCs). The main contribution is to lower the bus activity by an average 64.55&#x25; and thus decrease the IO power consumption through reconfiguring the MBUS transmission. This method is effective because field-programmable gate array (FPGA) IOs are most likely to have very large capacitance associated with them and consequently dissipate a lot of dynamic power. Experimental result shows an average 70.96&#x25; total power reduction compared with the original MBUS implementation.

X. Yang

N. Wu

J. H. Andrian

Comparative Power Analysis of an Adaptive Bus Encoding Method on the MBUS Structure

Oscillation-based testing (OBT) has been proven to be a simple, yet effective VLSI test for numerous circuit types. This paper investigates, for the first time, the application of OBT verification for second generation current conveyors (CCIIs). The OBT is formed by connecting the CCII into a simple Wien bridge oscillator and monitoring both the amplitude and frequency of oscillation. The fault detection rate, taking into account both the open and short circuit fault simulation analyses, indicates 96.34% fault coverage using a combination of amplitude and frequency output sensing in all technology corners. The only nondetected faults are short circuits between <svg xmlns:xlink="http://www.w3.org/1999/xlink" xmlns="http://www.w3.org/2000/svg" style="vertical-align:-3.1815pt" id="M1" height="11.8174pt" version="1.1" viewBox="-0.0498162 -8.6359 21.4848 11.8174" width="21.4848pt"><g transform="matrix(.013,0,0,-0.013,0,0)"><path id="g113-87" d="M697 650H468L461 623L492 619C539 613 547 605 518 546C481 471 367 264 278 116H276C239 278 197 500 186 567C180 604 185 613 226 619L252 623L260 650H24L17 623C78 617 92 613 108 533L216 -11H247C365 200 515 462 560 529C616 612 624 615 689 623L697 650Z"/></g><g transform="matrix(.0091,0,0,-0.0091,7.332,3.132)"><path id="g58-66" d="M43 650V617C122 612 130 606 130 522V128C130 44 122 37 34 32V0H275C400 0 497 25 573 82C652 142 698 229 698 350C698 445 662 518 613 565C549 625 456 650 327 650H43ZM217 544C217 580 220 591 229 599C240 607 264 613 311 613C380 613 437 599 482 570C561 523 598 436 598 336C598 177 511 40 324 40C248 40 217 61 217 135V544Z"/></g><g transform="matrix(.0091,0,0,-0.0091,14.038,3.132)"><use xlink:href="#g58-66"/></g></svg> and <svg xmlns:xlink="http://www.w3.org/1999/xlink" xmlns="http://www.w3.org/2000/svg" style="vertical-align:-3.2957pt" id="M2" height="11.9316pt" version="1.1" viewBox="-0.0498162 -8.6359 16.799 11.9316" width="16.799pt"><g transform="matrix(.013,0,0,-0.013,0,0)"><use xlink:href="#g113-87"/></g><g transform="matrix(.0091,0,0,-0.0091,7.332,3.132)"><path id="g58-81" d="M416 501L399 642C356 655 314 665 271 665C140 665 63 582 63 486C63 372 163 325 229 290C304 250 359 217 359 142C359 70 316 25 240 25C138 25 94 125 78 186L44 178C52 123 64 45 72 21C81 16 96 8 121 0S179 -15 220 -15C353 -15 445 68 445 176C445 289 350 335 270 375C191 414 143 449 143 520C143 572 177 627 253 627C340 627 366 556 382 495L416 501Z"/></g><g transform="matrix(.0091,0,0,-0.0091,11.736,3.132)"><use xlink:href="#g58-81"/></g></svg>, which can be detected using other techniques such as IDDQ testing. This method is found to be sensitive to resistor and capacitor process variation in the Wien bridge oscillator, but mitigating test steps are proposed.

Pablo Petrashin

Luis Toledo

Walter Lancioni

Piotr Osuch

Tinus Stander

Oscillation-Based Test Applied to a Wideband CCII

A classic second-order coupled-capacitor Chebyshev bandpass filter using resonator of tunable active capacitor and inductor is presented. The low cost and small size of CMOS active components make the bandpass filter (BPF) attractive in fully integrated CMOS applications. The tunable active capacitor is designed to compensate active inductor’s resistance for resistive match in the resonator. In many design cases, more than 95% resistive loss is cancelled. Meanwhile, adjusting design parameter of the active component provides BPF tunability in center frequency, pass band, and pass band gain. Designed in 1.8 V 180 nanometer CMOS process, the BPF has a tuning frequency range of 758–864 MHz, a controllable pass band of 7.1–65.9 MHz, a quality factor <svg xmlns:xlink="http://www.w3.org/1999/xlink" xmlns="http://www.w3.org/2000/svg" style="vertical-align:-2.150701pt" id="M1" height="10.7866pt" version="1.1" viewBox="-0.0498162 -8.6359 9.52083 10.7866" width="9.52083pt"><g transform="matrix(.013,0,0,-0.013,0,0)"><path id="g113-82" d="M699 368C699 549 574 666 407 666C186 666 23 488 23 277C23 113 129 -3 288 -13L307 -26C431 -111 501 -139 533 -147C559 -154 613 -163 658 -164L666 -141C597 -111 507 -66 430 -11L416 -1C580 42 699 190 699 368ZM601 371C601 227 518 54 381 22L354 40L278 24C175 47 120 145 120 269C120 451 235 631 398 631C540 631 601 521 601 371Z"/></g></svg> of 12–107, a pass band gain of 6.5–18.1 dB, and a stopband rejection of 38–50 dB.

Yu Wang

Jian Chen

Chien-In Henry Chen

Chebyshev Bandpass Filter Using Resonator of Tunable Active Capacitor and Inductor

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