Nowadays, many new low power ASICs applications have emerged. This new market trend made the designer&#x2019;s task of meeting the timing and routability requirements within the power budget more challenging. One of the major sources of power consumption in modern integrated circuits (ICs) is the Interconnect. In this paper, we present a novel Power and Timing-Driven global Placement (PTDP) algorithm. Its principle is to wrap a commercial timing-driven placer with a nets weighting mechanism to calculate the nets weights based on their timing and power consumption. The new calculated weight is used to drive the placement engine to place the cells connected by the critical power or timing nets close to each other and hence reduce the parasitic capacitances of the interconnects and, by consequence, improve the timing and power consumption of the design. This approach not only improves the design power consumption but facilitates also the routability with only a minor impact on the timing closure of a few designs. The experiments carried on 40 industrial designs of different nodes, sizes, and complexities and demonstrate that the proposed algorithm is able to achieve significant improvements on Quality of Results (QoR) compared with a commercial timing driven placement flow. We effectively reduce the interconnect power by an average of 11.5&#x25; that leads to a total power improvement of 5.4&#x25;, a timing improvement of 9.4&#x25;, 13.7&#x25;, and of 3.2&#x25; in Worst Negative Slack (WNS), Total Negative Slack (TNS), and total wirelength reduction, respectively.

Mohamed Chentouf

Zine El Abidine Alaoui Ismaili

A Novel Net Weighting Algorithm for Power and Timing-Driven Placement

Due to demand of information transfer through higher speed wireless communication network, it is time to think about security of important information to be transferred. Further, as these communication networks are part of open channel, to preserve the security of any Critical Information (CI) is really a challenging task in any real-time application. Data hiding techniques give more security and robustness of important CI against encryption or cryptographic software solutions. However, hardwired approach exhibits better solution not only in terms of reduction of complexity but also in terms of adaptive real-time output. This paper demonstrates frequency, Discrete Cosine Transform (DCT) domain Steganographic data hiding hardware solution for secret communication called Crypto-Stego-Real-Time (CSRT) System. The challenge is to design a secure algorithm keeping reliability of minimum distortion of original cover signal while embedding considerable amount of CI. Field Programmable Gate Array (FPGA) implementation shown in this paper is more secure, robust, and fast. Pipelining process while embedding enhances the speed of embedding, optimizes the memory utilization, and gives better Peak Signal to Noise Ratio (PSNR) and high robustness. Practically implemented hardware Steganographic solutions shown in this paper also give better performance than that of the current state-of-the-art hardware implementations.

Latika Desai

Suresh Mali

Crypto-Stego-Real-Time (CSRT) System for Secure Reversible Data Hiding

Wireless capsule endoscopy (WCE) is a painless diagnostic tool used by the physicians for endoscopic examination of the gastrointestinal track. The performance of the existing WCE systems is limited by high power consumption and low data rate transmission. In this paper, a 144&#x2009;MHz FinFET On-Off Keying (OOK) transmitter is designed and integrated with a class-E power amplifier. It is implemented and simulated using 16&#x2009;nm FinFET Predictive Technology Models. The proposed transmitter can achieve the data rate of 33&#x2009;Mbps with average power consumption of 1.04&#x2009;mW from a 0.85&#x2009;V power supply in the simulation. This design outperforms the current state-of-the-art designs.

Ioannis Intzes

Hongying Meng

John P. Cosmas

High Data Rate FinFET On-Off Keying Transmitter for Wireless Capsule Endoscopy

Timing optimization for logic circuits is one of the key steps in logic synthesis. Extant research data are mainly proposed based on various intelligence algorithms. Hence, they are neither comparable with timing optimization data collected by the mainstream electronic design automation (EDA) tool nor able to verify the superiority of intelligence algorithms to the EDA tool in terms of optimization ability. To address these shortcomings, a novel verification method is proposed in this study. First, a discrete particle swarm optimization (DPSO) algorithm was applied to optimize the timing of the mixed polarity Reed-Muller (MPRM) logic circuit. Second, the Design Compiler (DC) algorithm was used to optimize the timing of the same MPRM logic circuit through special settings and constraints. Finally, the timing optimization results of the two algorithms were compared based on MCNC benchmark circuits. The timing optimization results obtained using DPSO are compared with those obtained from DC, and DPSO demonstrates an average reduction of 9.7&#x25; in the timing delays of critical paths for a number of MCNC benchmark circuits. The proposed verification method directly ascertains whether the intelligence algorithm has a better timing optimization ability than DC.

Chuandong Chen

Rongshan Wei

Shaohao Wang

Wei Hu

Novel Verification Method for Timing Optimization Based on DPSO

The physical constraints of ever-shrinking CMOS transistors are rapidly approaching atomistic and quantum mechanical limits. Therefore, research is now directed towards the development of nanoscale devices that could work efficiently in the sub-10&#x2009;nm regime. This coupled with the fact that recent design trend for analog signal processing applications is moving towards current-mode circuits which offer lower voltage swings, higher bandwidth, and better signal linearity is the motivation for this work. A digitally controlled DVCC has been realized using CNFETs. This work exploited the CNFET&#x2019;s parameters like chirality, pitch, and numbers of CNTs to perform the digital control operation. The circuit has minimum number of transistors and can control the output current digitally. A similar CMOS circuit with 32&#x2009;nm CMOS parameters was also simulated and compared. The result shows that CMOS-based circuit requires 418.6&#x2009;<i>&#x3bc;</i>W while CNFET-based circuit consumes 352.1&#x2009;<i>&#x3bc;</i>W only. Further, the proposed circuit is used to realize a CNFET-based instrumentation amplifier with digitally programmable gain. The amplifier has a CMRR of 100&#x2009;dB and ICMR equal to 0.806&#x2009;V. The 3&#x2009;dB bandwidth of the amplifier is 11.78&#x2009;GHz which is suitable for the applications like navigation, radar instrumentation, and high-frequency signal amplification and conditioning.

S. K. Tripathi

Mohd. Samar Ansari

Amit M. Joshi

Carbon Nanotubes-Based Digitally Programmable Current Follower

Synthesis of reversible sequential circuits is a very new research area. It has been shown that such circuits can be implemented using quantum dot cellular automata. Other work has used traditional designs for sequential circuits and replaced the flip-flops and the gates with their reversible counterparts. Our earlier work uses a direct feedback method without any flip-flops, improving upon the replacement technique in both quantum cost and ancilla inputs. We present here a further improved version of the direct feedback method. Design examples show that the proposed method produces better results than our earlier method in terms of both quantum cost and ancilla inputs. We also propose the first technique for online testing of single line faults in sequential reversible circuits.

Mozammel H. A. Khan

Jacqueline E. Rice

First Steps in Creating Online Testable Reversible Sequential Circuits

Recently, we present a novel Mastrovito form of nonrecursive Karatsuba multiplier for all trinomials. Specifically, we found that related Mastrovito matrix is very simple for equally spaced trinomial (EST) combined with classic Karatsuba algorithm (KA), which leads to a highly efficient Karatsuba multiplier. In this paper, we consider a new special class of irreducible trinomial, namely, <span class="inline_break"><svg xmlns:xlink="http://www.w3.org/1999/xlink" xmlns="http://www.w3.org/2000/svg" width="25.655pt" style="vertical-align:-0.3499002pt" id="M1" height="12.6081pt" version="1.1" viewBox="-0.0498162 -12.2582 25.655 12.6081"><g transform="matrix(.013,0,0,-0.013,0,0)"><path id="g113-121" d="M536 404C536 423 520 448 491 448C445 448 398 404 308 283L286 338C255 416 242 448 217 448C182 448 138 402 92 341L111 321C149 368 169 378 178 378C188 378 198 363 214 320L254 212C185 117 138 65 107 65C98 65 85 69 82 75C79 82 73 86 65 86C44 86 23 60 23 39C23 7 44 -12 71 -12C119 -12 168 33 265 177L306 61C321 17 347 -12 373 -12C413 -12 465 33 507 96L491 119C459 84 432 60 413 60C395 60 378 92 358 148L321 250C341 279 369 310 389 332C417 363 439 382 456 382C466 382 475 376 481 368C486 361 492 358 496 358C513 358 536 381 536 404Z"/></g><g transform="matrix(.0091,0,0,-0.0091,7.267,-5.741)"><path id="g50-110" d="M781 91L765 118C733 86 702 70 693 70C686 70 685 77 692 106L738 297C772 439 736 451 712 451S675 445 647 431C605 410 526 356 452 257H450L459 294C491 426 459 451 429 451C403 451 386 445 361 431C312 404 239 343 170 253H168L188 333C208 411 205 451 175 451C148 451 85 417 24 346L39 318C57 338 100 374 112 374C120 374 122 372 115 339C91 226 62 112 28 -6L37 -12C59 -4 87 3 114 6C125 68 142 127 154 168C184 227 316 383 372 383C397 383 396 366 381 289C362 192 338 92 312 -6L317 -12C339 -5 367 3 396 6L434 170C468 234 598 383 650 383C668 383 676 369 664 319L609 90C593 23 600 -12 629 -12C654 -12 722 23 781 91Z"/></g><g transform="matrix(.013,0,0,-0.013,18.024,0)"><path id="g117-36" d="M535 230V280H323V490H265V280H52V230H265V-3H323V230H535Z"/></g></svg><span class="ibiop"></span><svg xmlns:xlink="http://www.w3.org/1999/xlink" xmlns="http://www.w3.org/2000/svg" width="34.022pt" style="vertical-align:-0.3499002pt" height="12.6081pt" version="1.1" viewBox="28.5101838 -12.2582 34.022 12.6081"><g transform="matrix(.013,0,0,-0.013,28.56,0)"><use xlink:href="#g113-121"/></g><g transform="matrix(.0091,0,0,-0.0091,35.828,-5.741)"><use xlink:href="#g50-110"/></g><g transform="matrix(.0091,0,0,-0.0091,43.153,-5.741)"><path id="g50-48" d="M381 704H317L48 -163H112L381 704Z"/></g><g transform="matrix(.0091,0,0,-0.0091,47.061,-5.741)"><path id="g50-52" d="M290 377C321 398 342 415 358 430C378 450 389 473 389 502C389 578 329 635 238 635H237C184 635 137 610 109 578L64 515L88 493C112 529 154 573 208 573S303 542 303 482C303 409 233 370 141 341L149 308C165 313 190 319 215 319C272 319 341 283 341 193C342 98 292 43 222 43C163 43 122 72 96 94C88 101 79 100 70 94C61 87 47 73 46 60C44 47 48 37 62 23C76 10 118 -12 165 -12C238 -12 430 62 430 223C430 297 379 359 290 375V377Z"/></g><g transform="matrix(.013,0,0,-0.013,54.951,0)"><use xlink:href="#g117-36"/></g></svg><span class="ibiop"></span><svg xmlns:xlink="http://www.w3.org/1999/xlink" xmlns="http://www.w3.org/2000/svg" width="6.475pt" style="vertical-align:-0.3499002pt" height="12.6081pt" version="1.1" viewBox="65.4371838 -12.2582 6.475 12.6081"><g transform="matrix(.013,0,0,-0.013,65.487,0)"><path id="g113-50" d="M384 0V27C293 34 287 42 287 114V635C232 613 172 594 109 583V559L157 557C201 555 205 550 205 499V114C205 42 199 34 109 27V0H384Z"/></g></svg></span>. Based on a three-term KA and shifted polynomial basis (SPB), a novel bit-parallel multiplier is derived with better space and time complexity. As a main contribution, the proposed multiplier costs about <span class="inline_break"><svg xmlns:xlink="http://www.w3.org/1999/xlink" xmlns="http://www.w3.org/2000/svg" width="11.596pt" style="vertical-align:-2.15067pt" id="M2" height="11.439pt" version="1.1" viewBox="-0.0498162 -9.28833 11.596 11.439"><g transform="matrix(.013,0,0,-0.013,0,0)"><path id="g113-51" d="M412 140C382 77 369 73 315 73H129L270 222C362 320 402 379 402 466C402 571 322 635 234 635C177 635 130 609 99 576L42 495L64 475C90 514 133 568 201 568C274 568 318 519 318 435C318 349 255 267 193 193C144 135 87 78 32 23V0H405C417 45 427 89 440 131L412 140Z"/></g><g transform="matrix(.013,0,0,-0.013,6.24,0)"><path id="g113-48" d="M368 703H309L44 -163H104L368 703Z"/></g></svg><span class="isep"/><svg xmlns:xlink="http://www.w3.org/1999/xlink" xmlns="http://www.w3.org/2000/svg" width="6.402pt" style="vertical-align:-2.15067pt" height="11.439pt" version="1.1" viewBox="11.5511838 -9.28833 6.402 11.439"><g transform="matrix(.013,0,0,-0.013,11.601,0)"><path id="g113-52" d="M285 378C315 398 338 416 353 432C373 451 384 474 384 503C384 579 325 635 236 635H235C182 635 136 610 108 579L65 516L85 496C110 533 150 575 205 575C258 575 300 543 300 481C300 407 232 369 141 339L147 310C163 315 188 321 211 321C268 321 338 284 338 192C338 94 288 40 217 40C160 40 119 68 93 91C85 98 77 97 69 91C60 84 47 71 46 58C44 46 48 35 62 22C75 10 116 -12 162 -12C234 -12 424 62 424 224C424 297 373 359 285 376V378Z"/></g></svg></span> circuit gates of the fastest multipliers, while its time delay matches our former result. To the best of our knowledge, this is the first time that the space complexity bound is reached without increasing the gate delay.

Yin Li

Yu Zhang

Xiaoli Guo

Efficient Nonrecursive Bit-Parallel Karatsuba Multiplier for a Special Class of Trinomials

About this journal

Journal profile

Meet the editorial board

Editor spotlight

Submit your proposal

Do you think there is an emerging area of research that really needs to be highlighted? Or an existing research area that has been overlooked or would benefit from deeper investigation? Raise the profile of a research area by leading a Special Issue.

VLSI Design