VLSI Design https://www.hindawi.com The latest articles from Hindawi © 2017 , Hindawi Limited . All rights reserved. Oscillation-Based Test Applied to a Wideband CCII Wed, 24 May 2017 07:14:25 +0000 http://www.hindawi.com/journals/vlsi/2017/5075103/ Oscillation-based testing (OBT) has been proven to be a simple, yet effective VLSI test for numerous circuit types. This paper investigates, for the first time, the application of OBT verification for second generation current conveyors (CCIIs). The OBT is formed by connecting the CCII into a simple Wien bridge oscillator and monitoring both the amplitude and frequency of oscillation. The fault detection rate, taking into account both the open and short circuit fault simulation analyses, indicates 96.34% fault coverage using a combination of amplitude and frequency output sensing in all technology corners. The only nondetected faults are short circuits between and , which can be detected using other techniques such as IDDQ testing. This method is found to be sensitive to resistor and capacitor process variation in the Wien bridge oscillator, but mitigating test steps are proposed. Pablo Petrashin, Luis Toledo, Walter Lancioni, Piotr Osuch, and Tinus Stander Copyright © 2017 Pablo Petrashin et al. All rights reserved. Chebyshev Bandpass Filter Using Resonator of Tunable Active Capacitor and Inductor Thu, 18 May 2017 00:00:00 +0000 http://www.hindawi.com/journals/vlsi/2017/5369167/ A classic second-order coupled-capacitor Chebyshev bandpass filter using resonator of tunable active capacitor and inductor is presented. The low cost and small size of CMOS active components make the bandpass filter (BPF) attractive in fully integrated CMOS applications. The tunable active capacitor is designed to compensate active inductor’s resistance for resistive match in the resonator. In many design cases, more than 95% resistive loss is cancelled. Meanwhile, adjusting design parameter of the active component provides BPF tunability in center frequency, pass band, and pass band gain. Designed in 1.8 V 180 nanometer CMOS process, the BPF has a tuning frequency range of 758–864 MHz, a controllable pass band of 7.1–65.9 MHz, a quality factor of 12–107, a pass band gain of 6.5–18.1 dB, and a stopband rejection of 38–50 dB. Yu Wang, Jian Chen, and Chien-In Henry Chen Copyright © 2017 Yu Wang et al. All rights reserved. A 69-dB SNR 89-μW AGC for Multifrequency Signal Processing Based on Peak-Statistical Algorithm and Judgment Logic Thu, 29 Dec 2016 11:26:25 +0000 http://www.hindawi.com/journals/vlsi/2016/6708253/ A novel peak-statistical algorithm and judgment logic (PSJ) for multifrequency signal application of Autogain Control Loop (AGC) in hearing aid SoC is proposed in this paper. Under a condition of multifrequency signal, it tracks the amplitude change and makes statistical data of them. Finally, the judgment is decided and the circuit gain is controlled precisely. The AGC circuit is implemented with 0.13 μm 1P8M CMOS mixed-signal technology. Meanwhile, the low-power circuit topology and noise-optimizing technique are adopted to improve the signal-to-noise ratio (SNR) of our circuit. Under 1 V voltage supply, the peak SNR achieves 69.2 dB and total harmonic distortion (THD) is 65.3 dB with 89 μW power consumption. Lan Dai and Chengying Chen Copyright © 2016 Lan Dai and Chengying Chen. All rights reserved. FuMicro: A Fused Microarchitecture Design Integrating In-Order Superscalar and VLIW Thu, 15 Dec 2016 14:20:23 +0000 http://www.hindawi.com/journals/vlsi/2016/8787919/ This paper proposes FuMicro, a fused microarchitecture integrating both in-order superscalar and Very Long Instruction Word (VLIW) in a single core. A processor with FuMicro microarchitecture can work under alternative in-order superscalar and VLIW mode, using the same pipeline and the same Instruction Set Architecture (ISA). Small modification to the compiler is made to expand the register file in VLIW mode. The decision of mode switch is made by software, and this does not need extra hardware. VLIW code can be exploited in the form of library function and the users will be exposed under only superscalar mode; by this means, we can provide the users with a convenient development environment. FuMicro could serve as a universal microarchitecture for it can be applied to different ISAs. In this paper, we focus on the implementation of FuMicro with ARM ISA. This architecture is evaluated on gem5, which is a cycle accurate microarchitecture simulation platform. By adopting FuMicro microarchitecture, the performance can be improved on an average of 10%, with the best performance improvement being 47.3%, compared with that under pure in-order superscalar mode. The result shows that FuMicro microarchitecture can improve Instruction Level Parallelism (ILP) significantly, making it promising to expand digital signal processing capability on a General Purpose Processor. Yumin Hou, Hu He, Xu Yang, Deyuan Guo, Xu Wang, Jiawei Fu, and Keni Qiu Copyright © 2016 Yumin Hou et al. All rights reserved. A Cache System Design for CMPs with Built-In Coherence Verification Sun, 30 Oct 2016 10:22:41 +0000 http://www.hindawi.com/journals/vlsi/2016/8093614/ This work reports an effective design of cache system for Chip Multiprocessors (CMPs). It introduces built-in logic for verification of cache coherence in CMPs realizing directory based protocol. It is developed around the cellular automata (CA) machine, invented by John von Neumann in the 1950s. A special class of CA referred to as single length cycle 2-attractor cellular automata (TACA) has been planted to detect the inconsistencies in cache line states of processors’ private caches. The TACA module captures coherence status of the CMPs’ cache system and memorizes any inconsistent recording of the cache line states during the processors’ reference to a memory block. Theory has been developed to empower a TACA to analyse the cache state updates and then to settle to an attractor state indicating quick decision on a faulty recording of cache line status. The introduction of segmentation of the CMPs’ processor pool ensures a better efficiency, in determining the inconsistencies, by reducing the number of computation steps in the verification logic. The hardware requirement for the verification logic points to the fact that the overhead of proposed coherence verification module is much lesser than that of the conventional verification units and is insignificant with respect to the cost involved in CMPs’ cache system. Mamata Dalui and Biplab K. Sikdar Copyright © 2016 Mamata Dalui and Biplab K. Sikdar. All rights reserved. A Low Complexity All-Digital Background Calibration Technique for Time-Interleaved ADCs Sun, 09 Oct 2016 11:15:48 +0000 http://www.hindawi.com/journals/vlsi/2016/6475932/ A low complexity all-digital background calibration technique based on statistics is proposed. The basic idea of the statistics calibration technique is that the output average energy of each channel of TIADC will be consistent ideally, since each channel samples the same input signal, and therefore the energy deviation directly reflects the mismatch errors of channels. In this work, the offset mismatch and gain mismatch are calibrated by an adaptive statistics calibration algorithm based on LMS iteration; the timing mismatch is estimated by performing the correlation calculation of the outputs of subchannels and corrected by an improved fractional delay filter based on Farrow structure. Applied to a four-channel 12-bit 400 MHz TIADC, simulation results show that, with calibration, the SNDR raises from 22.5 dB to 71.8 dB and ENOB rises from 3.4 bits to 11.6 bits for a 164.6 MHz sinusoidal input. Compared with traditional methods, the proposed schemes are more feasible to implement and consume less hardware resources. Hongmei Chen, Yongsheng Yin, Honghui Deng, and Fujiang Lin Copyright © 2016 Hongmei Chen et al. All rights reserved. Unified and Modular Modeling and Functional Verification Framework of Real-Time Image Signal Processors Mon, 26 Sep 2016 10:58:58 +0000 http://www.hindawi.com/journals/vlsi/2016/7283471/ In VLSI industry, image signal processing algorithms are developed and evaluated using software models before implementation of RTL and firmware. After the finalization of the algorithm, software models are used as a golden reference model for the image signal processor (ISP) RTL and firmware development. In this paper, we are describing the unified and modular modeling framework of image signal processing algorithms used for different applications such as ISP algorithms development, reference for hardware (HW) implementation, reference for firmware (FW) implementation, and bit-true certification. The universal verification methodology- (UVM-) based functional verification framework of image signal processors using software reference models is described. Further, IP-XACT based tools for automatic generation of functional verification environment files and model map files are described. The proposed framework is developed both with host interface and with core using virtual register interface (VRI) approach. This modeling and functional verification framework is used in real-time image signal processing applications including cellphone, smart cameras, and image compression. The main motivation behind this work is to propose the best efficient, reusable, and automated framework for modeling and verification of image signal processor (ISP) designs. The proposed framework shows better results and significant improvement is observed in product verification time, verification cost, and quality of the designs. Abhishek Jain and Richa Gupta Copyright © 2016 Abhishek Jain and Richa Gupta. All rights reserved. New Proposal for MCML Based Three-Input Logic Implementation Mon, 19 Sep 2016 09:24:19 +0000 http://www.hindawi.com/journals/vlsi/2016/8712768/ This paper presents a new proposal for three-input logic function implementation in MOS current mode logic (MCML) style. The conventional realization of such logic employs three levels of stacked source-coupled transistor pairs. It puts restriction on minimum power supply requirement and results in increased static power. The new proposal presents a circuit element named as quad-tail cell which reduces number of stacked source-coupled transistor levels by two. A three-input exclusive-OR (XOR) gate, a vital element in digital system design, is chosen to elaborate the approach. Its behavior is analyzed and SPICE simulations using TSMC 180 nm CMOS technology parameters are included to support the theoretical concept. The performance of the proposed circuit is compared with its counterparts based on CMOS complementary pass transistor logic, conventional MCML, and cascading of existing two input tripple-tail XOR cells and applying triple-tail concept in conventional MCML topology. It is found that the proposed XOR gate performs best in terms of most of the performance parameters. The sensitivity of the proposed XOR gate towards process variation shows a variation of 1.54 between the best and worst case. As an extension, a realization of 4 : 1 multiplexer has also been included. Neeta Pandey, Kirti Gupta, and Bharat Choudhary Copyright © 2016 Neeta Pandey et al. All rights reserved. Improved Switching Energy Reduction Approach in Low-Power SAR ADC for Bioelectronics Mon, 22 Aug 2016 14:00:49 +0000 http://www.hindawi.com/journals/vlsi/2016/6029254/ Low-power analog-to-digital converter (ADC) is a crucial part of wearable or implantable bioelectronics. In order to reduce the power of successive-approximation-register (SAR) ADC, an improved energy-efficient capacitor switching scheme of SAR ADC is proposed for implantable bioelectronic applications. With sequence initialization, novel logic control, and capacitive subconversion, 97.6% switching energy is reduced compared to the traditional structure. Moreover, thanks to the top-plate sampling and capacitive subconversion, 87% input-capacitance reduction can be achieved over the conventional structure. A 10-bit SAR ADC with this proposed switching scheme is realized in 65 nm CMOS. With 1.514 KHz differential sinusoidal input signals sampled at 50 KS/s, the ADC achieves an SNDR of 61.4 dB and only consumes power of 450 nW. The area of this SAR ADC IP core is only 136 μm × 176 μm, making it also area-efficient and very suitable for biomedical electronics application. Xingyuan Tong and Tiantian Sun Copyright © 2016 Xingyuan Tong and Tiantian Sun. All rights reserved. An Efficient Reconfigurable Architecture for Fingerprint Recognition Thu, 28 Jul 2016 11:08:51 +0000 http://www.hindawi.com/journals/vlsi/2016/9532762/ The fingerprint identification is an efficient biometric technique to authenticate human beings in real-time Big Data Analytics. In this paper, we propose an efficient Finite State Machine (FSM) based reconfigurable architecture for fingerprint recognition. The fingerprint image is resized, and Compound Linear Binary Pattern (CLBP) is applied on fingerprint, followed by histogram to obtain histogram CLBP features. Discrete Wavelet Transform (DWT) Level 2 features are obtained by the same methodology. The novel matching score of CLBP is computed using histogram CLBP features of test image and fingerprint images in the database. Similarly, the DWT matching score is computed using DWT features of test image and fingerprint images in the database. Further, the matching scores of CLBP and DWT are fused with arithmetic equation using improvement factor. The performance parameters such as TSR (Total Success Rate), FAR (False Acceptance Rate), and FRR (False Rejection Rate) are computed using fusion scores with correlation matching technique for FVC2004 DB3 Database. The proposed fusion based VLSI architecture is synthesized on Virtex xc5vlx30T-3 FPGA board using Finite State Machine resulting in optimized parameters. Satish S. Bhairannawar, K. B. Raja, and K. R. Venugopal Copyright © 2016 Satish S. Bhairannawar et al. All rights reserved. Self-Healing Many-Core Architecture: Analysis and Evaluation Mon, 25 Jul 2016 14:32:30 +0000 http://www.hindawi.com/journals/vlsi/2016/9767139/ More pronounced aging effects, more frequent early-life failures, and incomplete testing and verification processes due to time-to-market pressure in new fabrication technologies impose reliability challenges on forthcoming systems. A promising solution to these reliability challenges is self-test and self-reconfiguration with no or limited external control. In this work a scalable self-test mechanism for periodic online testing of many-core processor has been proposed. This test mechanism facilitates autonomous detection and omission of faulty cores and makes graceful degradation of the many-core architecture possible. Several test components are incorporated in the many-core architecture that distribute test stimuli, suspend normal operation of individual processing cores, apply test, and detect faulty cores. Test is performed concurrently with the system normal operation without any noticeable downtime at the application level. Experimental results show that the proposed test architecture is extensively scalable in terms of hardware overhead and performance overhead that makes it applicable to many-cores with more than a thousand processing cores. Arezoo Kamran and Zainalabedin Navabi Copyright © 2016 Arezoo Kamran and Zainalabedin Navabi. All rights reserved. Implementation, Test Pattern Generation, and Comparative Analysis of Different Adder Circuits Wed, 08 Jun 2016 10:56:51 +0000 http://www.hindawi.com/journals/vlsi/2016/1260879/ Addition usually affects the overall performance of digital systems and an arithmetic function. Adders are most widely used in applications like multipliers, DSP (i.e., FFT, FIR, and IIR). In digital adders, the speed of addition is constrained by the time required to propagate a carry through the adder. Various techniques have been proposed to design fast adders. We have derived architectures for carry-select adder (CSA), Common Boolean Logic (CBL) based adders, ripple carry adder (RCA), and Carry Look-Ahead Adder (CLA) for 8-, 16-, 32-, and 64-bit length. In this work we have done comparative analysis of different types of adders in Synopsis Design Compiler using different standard cell libraries at 32/28 nm. Also, the designs are analyzed for the stuck at faults (s-a-0, s-a-1) using Synopsis TetraMAX. Vikas K. Saini, Shamim Akhter, and Tanuj Chauhan Copyright © 2016 Vikas K. Saini et al. All rights reserved. Shared Reed-Muller Decision Diagram Based Thermal-Aware AND-XOR Decomposition of Logic Circuits Wed, 27 Apr 2016 08:54:47 +0000 http://www.hindawi.com/journals/vlsi/2016/3191286/ The increased number of complex functional units exerts high power-density within a very-large-scale integration (VLSI) chip which results in overheating. Power-densities directly converge into temperature which reduces the yield of the circuit. An adverse effect of power-density reduction is the increase in area. So, there is a trade-off between area and power-density. In this paper, we introduce a Shared Reed-Muller Decision Diagram (SRMDD) based on fixed polarity AND-XOR decomposition to represent multioutput Boolean functions. By recursively applying transformations and reductions, we obtained a compact SRMDD. A heuristic based on Genetic Algorithm (GA) increases the sharing of product terms by judicious choice of polarity of input variables in SRMDD expansion and a suitable area and power-density trade-off has been enumerated. This is the first effort ever to incorporate the power-density as a measure of temperature estimation in AND-XOR expansion process. The results of logic synthesis are incorporated with physical design in CADENCE digital synthesis tool to obtain the floor-plan silicon area and power profile. The proposed thermal-aware synthesis has been validated by obtaining absolute temperature of the synthesized circuits using HotSpot tool. We have experimented with 29 benchmark circuits. The minimized AND-XOR circuit realization shows average savings up to 15.23% improvement in silicon area and up to 17.02% improvement in temperature over the sum-of-product (SOP) based logic minimization. Apangshu Das and Sambhu Nath Pradhan Copyright © 2016 Apangshu Das and Sambhu Nath Pradhan. All rights reserved. A Novel Time Synchronization Method for Dynamic Reconfigurable Bus Sun, 03 Apr 2016 06:08:41 +0000 http://www.hindawi.com/journals/vlsi/2016/5752080/ UM-BUS is a novel dynamically reconfigurable high-speed serial bus for embedded systems. It can achieve fault tolerance by detecting the channel status in real time and reconfigure dynamically at run-time. The bus supports direct interconnections between up to eight master nodes and multiple slave nodes. In order to solve the time synchronization problem among master nodes, this paper proposes a novel time synchronization method, which can meet the requirement of time precision in UM-BUS. In this proposed method, time is firstly broadcasted through time broadcast packets. Then, the transmission delay and time deviations via three handshakes during link self-checking and channel detection can be worked out referring to the IEEE 1588 protocol. Thereby, each node calibrates its own time according to the broadcasted time. The proposed method has been proved to meet the requirement of real-time time synchronization. The experimental results show that the synchronous precision can achieve a bias less than 20 ns. Zhang Weigong, Li Chao, Qiu Keni, Zhang Shaonan, and Chen Xianglong Copyright © 2016 Zhang Weigong et al. All rights reserved. Ultra-Low-Voltage Self-Body Biasing Scheme and Its Application to Basic Arithmetic Circuits Mon, 26 Oct 2015 06:16:56 +0000 http://www.hindawi.com/journals/vlsi/2015/540482/ The gate level body biasing (GLBB) is assessed in the context of ultra-low-voltage logic designs. To this purpose, a GLBB mirror full adder is implemented by using a commercial 45 nm bulk CMOS triple-well technology and compared to equivalent conventional zero body-biased CMOS and dynamic threshold voltage MOSFET (DTMOS) circuits under different running conditions. Postlayout simulations demonstrate that, at the parity of leakage power consumption, the GLBB technique exhibits a significant concurrent reduction of the energy per operation and the delay in comparison to the conventional CMOS and DTMOS approaches. The silicon area required by the GLBB full adder is halved with respect to the equivalent DTMOS implementation, but it is higher in comparison to conventional CMOS design. Performed analysis also proves that the GLBB solution exhibits a high level of robustness against temperature fluctuations and process variations. Ramiro Taco, Marco Lanuzza, and Domenico Albano Copyright © 2015 Ramiro Taco et al. All rights reserved. The Design of Low Noise Amplifiers in Deep Submicron CMOS Processes: A Convex Optimization Approach Tue, 13 Oct 2015 07:22:39 +0000 http://www.hindawi.com/journals/vlsi/2015/312639/ With continued process scaling, CMOS has become a viable technology for the design of high-performance low noise amplifiers (LNAs) in the radio frequency (RF) regime. This paper describes the design of RF LNAs using a geometric programming (GP) optimization method. An important challenge for RF LNAs designed at nanometer scale geometries is the excess thermal noise observed in the MOSFETs. An extensive survey of analytical models and experimental results reported in the literature is carried out to quantify the issue of excessive thermal noise for short-channel MOSFETs. Short channel effects such as channel-length modulation and velocity saturation effects are also accounted for in our optimization process. The GP approach is able to efficiently calculate the globally optimum solution. The approximations required to setup the equations and constraints to allow convex optimization are detailed. The method is applied to the design of inductive source degenerated common source amplifiers at the 90 nm and 180 nm technology nodes. The optimization results are validated through comparison with numerical simulations using Agilent’s Advanced Design Systems (ADS) software. David H. K. Hoe and Xiaoyu Jin Copyright © 2015 David H. K. Hoe and Xiaoyu Jin. All rights reserved. A Modularized Noise Analysis Method with Its Application in Readout Circuit Design Wed, 09 Sep 2015 07:14:14 +0000 http://www.hindawi.com/journals/vlsi/2015/593019/ A readout integrated circuit (ROIC) is a crucial part that determines the quality of imaging. In order to analyze the noise of a ROIC with distinct illustration of each noise source transferring, a modularized noise analysis method is proposed whose application is applied for a ROIC cell, where all the MOSFETs are optimized in subthreshold region, leading to the power dissipation 2.8 μW. The modularized noise analysis begins with the noise model built using transfer functions and afterwards presents the transfer process of noise in the form of matrix, through which we can describe the contribution of each noise source to the whole output noise clearly, besides optimizing the values of key components. The optimal noise performance is obtained under the limitation of layout area less than 30 μm × 30 μm, resulting in that the integration capacitor should be selected as 0.74 pF to achieve an optimal noise performance, the whole output noise reaching the minimum value at 74.1 μV. In the end transient simulations utilizing Verilog-A are carried out for comparisons. The results showing good agreement verify the feasibility of the method presented through matrix. Xiao Wang, Zelin Shi, and Baoshu Xu Copyright © 2015 Xiao Wang et al. All rights reserved. Analysis and Implementation of Kidney Stone Detection by Reaction Diffusion Level Set Segmentation Using Xilinx System Generator on FPGA Tue, 02 Jun 2015 08:21:48 +0000 http://www.hindawi.com/journals/vlsi/2015/581961/ Ultrasound imaging is one of the available imaging techniques used for diagnosis of kidney abnormalities, which may be like change in shape and position and swelling of limb; there are also other Kidney abnormalities such as formation of stones, cysts, blockage of urine, congenital anomalies, and cancerous cells. During surgical processes it is vital to recognize the true and precise location of kidney stone. The detection of kidney stones using ultrasound imaging is a highly challenging task as they are of low contrast and contain speckle noise. This challenge is overcome by employing suitable image processing techniques. The ultrasound image is first preprocessed to get rid of speckle noise using the image restoration process. The restored image is smoothened using Gabor filter and the subsequent image is enhanced by histogram equalization. The preprocessed image is achieved with level set segmentation to detect the stone region. Segmentation process is employed twice for getting better results; first to segment kidney portion and then to segment the stone portion, respectively. In this work, the level set segmentation uses two terms, namely, momentum and resilient propagation () to detect the stone portion. After segmentation, the extracted region of the kidney stone is given to Symlets, Biorthogonal (bio3.7, bio3.9, and bio4.4), and Daubechies lifting scheme wavelet subbands to extract energy levels. These energy levels provide evidence about presence of stone, by comparing them with that of the normal energy levels. They are trained by multilayer perceptron (MLP) and back propagation (BP) ANN to classify and its type of stone with an accuracy of 98.8%. The prosed work is designed and real time is implemented on both Filed Programmable Gate Array Vertex-2Pro FPGA using Xilinx System Generator (XSG) Verilog and Matlab 2012a. Kalannagari Viswanath and Ramalingam Gunasundari Copyright © 2015 Kalannagari Viswanath and Ramalingam Gunasundari. All rights reserved. Functional Testbench Qualification by Mutation Analysis Thu, 07 May 2015 13:40:07 +0000 http://www.hindawi.com/journals/vlsi/2015/256474/ The growing complexity and higher time-to-market pressure make the functional verification of modern large scale hardware systems more challenging. These challenges bring the requirement of a high quality testbench that is capable of thoroughly verifying the design. To reveal a bug, the testbench needs to activate it by stimulus, propagate the erroneous behaviors to some checked points, and detect it at these checked points by checkers. However, current dominant verification approaches focus only on the activation aspect using a coverage model which is not qualified and ignore the propagation and detection aspects. Using a new metric, this paper qualifies the testbench by mutation analysis technique with the consideration of the quality of the stimulus, the coverage model, and the checkers. Then the testbench is iteratively refined according to the qualification feedback. We have conducted experiments on two designs of different scales to demonstrate the effectiveness of the proposed method in improving the quality of the testbench. Kai Huang, Peng Zhu, Rongjie Yan, and Xiaolang Yan Copyright © 2015 Kai Huang et al. All rights reserved. A Discrete Event System Approach to Online Testing of Speed Independent Circuits Thu, 30 Apr 2015 13:00:27 +0000 http://www.hindawi.com/journals/vlsi/2015/651785/ With the increase in soft failures in deep submicron ICs, online testing is becoming an integral part of design for testability. Some techniques for online testing of asynchronous circuits are proposed in the literature, which involves development of a checker that verifies the correctness of the protocol. This checker involves Mutex blocks making its area overhead quite high. In this paper, we have adapted the Theory of Fault Detection and Diagnosis available in the literature on Discrete Event Systems to online testing of speed independent asynchronous circuits. The scheme involves development of a state based model of the circuit, under normal and various stuck-at fault conditions, and finally designing state estimators termed as detectors. The detectors monitor the circuit online and determine whether it is functioning in normal/failure mode. The main advantages are nonintrusiveness and low area overheads compared to similar schemes reported in the literature. P. K. Biswal, K. Mishra, S. Biswas, and H. K. Kapoor Copyright © 2015 P. K. Biswal et al. All rights reserved. A Novel Scan Architecture for Low Power Scan-Based Testing Wed, 22 Apr 2015 07:45:40 +0000 http://www.hindawi.com/journals/vlsi/2015/264071/ Test power has been turned to a bottleneck for test considerations as the excessive power dissipation has serious negative effects on chip reliability. In scan-based designs, rippling transitions caused by test patterns shifting along the scan chain not only elevate power consumption but also introduce spurious switching activities in the combinational logic. In this paper, we propose a novel area-efficient gating scan architecture that offers an integrated solution for reducing total average power in both scan cells and combinational part during shift mode. In the proposed gating scan structure, conventional master/slave scan flip-flop has been modified into a new gating scan cell augmented with state preserving and gating logic that enables average power reduction in combinational logic during shift mode. The new gating scan cells also mitigate the number of transitions during shift and capture cycles. Thus, it contributes to average power reduction inside the scan cell during scan shifting with low impact on peak power during capture cycle. Simulation results have shown that the proposed gating scan cell saves 28.17% total average power compared to conventional scan cell that has no gating logic and up to 44.79% compared to one of the most common existing gating architectures. Mahshid Mojtabavi Naeini and Chia Yee Ooi Copyright © 2015 Mahshid Mojtabavi Naeini and Chia Yee Ooi. All rights reserved. Process Variation Aware Wide Tuning Band Pass Filter for Steep Roll-Off High Rejection Wed, 15 Apr 2015 11:56:34 +0000 http://www.hindawi.com/journals/vlsi/2015/408035/ A wide tuning band pass filter (BPF) with steep roll-off high rejection and low noise figure is presented. The design feature of steep roll-off high stopband rejection (>20 dB) and low noise figure (<6 dB) provides a wide tuning frequency span (1–2.04 GHz) to accept desirable signals and reject close interfering signals. The process variation aware design approach demonstrates robustness of the BPF after calibration from process variations, operating in 1.04 GHz tuning frequency span: almost zero deviation on center frequency, an average maximum deviation 1.16 dB on a nominal pass band gain of 55.6 dB, and an average maximum deviation 1.06 MHz on a nominal bandwidth of 12.3 MHz. Jian Chen and Chien-In Henry Chen Copyright © 2015 Jian Chen and Chien-In Henry Chen. All rights reserved. A New CDS Structure for High Density FPA with Low Power Sun, 01 Feb 2015 12:50:22 +0000 http://www.hindawi.com/journals/vlsi/2015/767161/ Being an essential part of infrared readout integrated circuit, correlated double sampling (CDS) circuits play important roles in both depressing reset noise and conditioning integration signals. To adapt applications for focal planes of large format and high density, a new structure of CDS circuit occupying small layout area is proposed, whose power dissipation has been optimized by using MOSFETs in operation of subthreshold region, which leads to 720 nW. Then the noise calculation model is established, based on which the noise analysis has been carried out by the approaches of transfer function and numerical simulations using SIMULINK and Verilog-A. The results are in good agreement, demonstrating the validity of the present noise calculation model. Thermal noise plays a dominant role in the long wave situation while noise is the majority in the medium wave situation. The total noise of long wave is smaller than medium wave, both of which increase with the integration capacitor and integration time increasing. Xiao Wang and Zelin Shi Copyright © 2015 Xiao Wang and Zelin Shi. All rights reserved. Advanced VLSI Architecture Design for Emerging Digital Systems Mon, 22 Dec 2014 09:55:38 +0000 http://www.hindawi.com/journals/vlsi/2014/746132/ Yu-Cheng Fan, Qiaoyan Yu, Thomas Schumann, Ying-Ren Chien, and Chih-Cheng Lu Copyright © 2014 Yu-Cheng Fan et al. All rights reserved. Investigation of a Superscalar Operand Stack Using FO4 and ASIC Wire-Delay Metrics Thu, 18 Dec 2014 00:10:21 +0000 http://www.hindawi.com/journals/vlsi/2014/493189/ Complexity in processor microarchitecture and the related issues of power density, hot spots and wire delay, are seen to be a major concern for design migration into low nanometer technologies of the future. This paper evaluates the hardware cost of an alternative to register-file organization, the superscalar stack issue array (SSIA). We believe this is the first such reported study using discrete stack elements. Several possible implementations are evaluated, using a 90 nm standard cell library as a reference model, yielding delay data and FO4 metrics. The evaluation, including reference to ASIC layout, RC extraction, and timing simulation, suggests a 4-wide issue rate of at least four Giga-ops/sec at 90 nm and opportunities for twofold future improvement by using more advanced design approaches. Christopher Bailey and Brendan Mullane Copyright © 2014 Christopher Bailey and Brendan Mullane. All rights reserved. On the Use of an Algebraic Signature Analyzer for Mixed-Signal Systems Testing Sun, 16 Nov 2014 00:00:00 +0000 http://www.hindawi.com/journals/vlsi/2014/465907/ We propose an approach to design of an algebraic signature analyzer that can be used for mixed-signal systems testing. The analyzer does not contain carry propagating circuitry, which improves its performance as well as fault tolerance. The common design technique of a signature analyzer for mixed-signal systems is based on the rules of an arithmetic finite field. The application of this technique to the systems with an arbitrary radix is a challenging task and the devices designed possess high hardware complexity. The proposed technique is simple and applicable to systems of any size and radix. The hardware complexity is low. The technique can also be used in arithmetic/algebraic coding and cryptography. Vadim Geurkov and Lev Kirischian Copyright © 2014 Vadim Geurkov and Lev Kirischian. All rights reserved. High-Efficient Circuits for Ternary Addition Mon, 01 Sep 2014 05:09:51 +0000 http://www.hindawi.com/journals/vlsi/2014/534587/ New ternary adders, which are fundamental components of ternary addition, are presented in this paper. They are on the basis of a logic style which mostly generates binary signals. Therefore, static power dissipation reaches its minimum extent. Extensive different analyses are carried out to examine how efficient the new designs are. For instance, the ternary ripple adder constructed by the proposed ternary half and full adders consumes 2.33 μW less power than the one implemented by the previous adder cells. It is almost twice faster as well. Due to their unique superior characteristics for ternary circuitry, carbon nanotube field-effect transistors are used to form the novel circuits, which are entirely suitable for practical applications. Reza Faghih Mirzaee, Keivan Navi, and Nader Bagherzadeh Copyright © 2014 Reza Faghih Mirzaee et al. All rights reserved. Engineering Change Orders Design Using Multiple Variables Linear Programming for VLSI Design Sun, 24 Aug 2014 11:40:10 +0000 http://www.hindawi.com/journals/vlsi/2014/698041/ An engineering change orders design using multiple variable linear programming for VLSI design is presented in this paper. This approach addresses the main issues of resource between spare cells and target cells. We adopt linear programming technique to plan and balance the spare cells and target cells to meet the new specification according to logic transformation. The proposed method solves the related problem of resource for ECO problems and provides a well solution. The scheme shows new concept to manage the spare cells to meet possible target cells for ECO research. Yu-Cheng Fan, Chih-Kang Lin, Shih-Ying Chou, Chun-Hung Wang, Shu-Hsien Wu, and Hung-Kuan Liu Copyright © 2014 Yu-Cheng Fan et al. All rights reserved. Design of Smart Power-Saving Architecture for Network on Chip Wed, 06 Aug 2014 11:22:49 +0000 http://www.hindawi.com/journals/vlsi/2014/531653/ In network-on-chip (NoC), the data transferring by virtual channels can avoid the issue of data loss and deadlock. Many virtual channels on one input or output port in router are included. However, the router includes five I/O ports, and then the power issue is very important in virtual channels. In this paper, a novel architecture, namely, Smart Power-Saving (SPS), for low power consumption and low area in virtual channels of NoC is proposed. The SPS architecture can accord different environmental factors to dynamically save power and optimization area in NoC. Comparison with related works, the new proposed method reduces 37.31%, 45.79%, and 19.26% on power consumption and reduces 49.4%, 25.5% and 14.4% on area, respectively. Trong-Yen Lee and Chi-Han Huang Copyright © 2014 Trong-Yen Lee and Chi-Han Huang. All rights reserved. Design of Synthesizable, Retimed Digital Filters Using FPGA Based Path Solvers with MCM Approach: Comparison and CAD Tool Thu, 24 Jul 2014 11:25:02 +0000 http://www.hindawi.com/journals/vlsi/2014/280701/ Retiming is a transformation which can be applied to digital filter blocks that can increase the clock frequency. This transformation requires computation of critical path and shortest path at various stages. In literature, this problem is addressed at multiple points. However, very little attention is given to path solver blocks in retiming transformation algorithm which takes up most of the computation time. In this paper, we address the problem of optimizing the speed of path solvers in retiming transformation by introducing high level synthesis of path solver algorithm architectures on FPGA and a computer aided design tool. Filters have their combination blocks as adders, multipliers, and delay elements. Avoiding costly multipliers is very much needed for filter hardware implementation. This can be achieved efficiently by using multiplierless MCM technique. In the present work, retiming which is a high level synthesis optimization method is combined with multiplierless filter implementations using MCM algorithm. It is seen that retiming multiplierless designs gives better performance in terms of operating frequency. This paper also compares various retiming techniques for multiplierless digital filter design with respect to VLSI performance metrics such as area, speed, and power. Deepa Yagain and A. Vijaya Krishna Copyright © 2014 Deepa Yagain and A. Vijaya Krishna. All rights reserved.