the design integr fault detector onlin test linear analog system discuss paper the method consist concurr process avail node voltag signal provid residu onlin carri inform about fault contrari few previous work deal particular case state variabl analog system method propos here useabl without limit larger class linear analog system even when state variabl avail measur voltag for purpos algorithm provid extend state space model ani linear analog system from it netlist descript develop implement

Emmanuel  Simeu

Optimal Detector Design for On-line Testing of Linear Analog Systems

paper new method transform given combin circuit selfdual circuit base notion selfdual complement investig the larg varieti selfdual complement can util optim transform selfdual circuit selfdual duplic selfdual pariti predict consid detail method reduct selfdual output output space compact selfdual output consid for first time also describ paper how selfdual circuit can modifi selfdual faultsecur circuit

A. Dmitriev

V. Saposhnikov

Vl. Saposhnikov

M. Goessel

Vl. Moshanin

A. Morosov

New Self-dual Circuits for Error Detection and Testing

this paper present novel method design total selfcheck tsc outof code checker take account realist fault model includ stuckat transistor stuckon transistor stuckopen resist bridg fault break the propos design method first method open literatur take account realist fault model can appli most practic valu apart from abov propos checker veri compact veri fast the singl output checker near optim respect number transistor requir implement another benefit propos tsc checker all fault test veri small set singl pattern test thus probabl achiev tsc goal greater than checker requir twopattern test the singl output tsc checker propos paper first known singl output tsc checker outof code

X.  Kavousianos

D.  Nikolos

G.  Sidiropoulos

Novel Single and Double Output TSC CMOS Checkers for m-out-of-n Codes

method selfcheck synchron finit state machin fsm network design low overhead develop checker use onli fsms which output line same time output line network the checker observ output line fsms the method base reduc problem selfcheck synchron fsm design the latter provid appli special descript fsm name socal unat programm logic array pla descript singl stuckat fault fsm pole gate pole consid pla realiz fsm allow factor multilevel logic synthesi they both provid unidirect manifest abov mention fault output line correspond fsms this realiz also give rise transpar each compon fsm network fault pla realiz deriv from state transit graph stg descript fsms use outof encod it state insignific expand product stg the problem replac arbitrari synchron fsm network selfcheck one low overhead discuss

A. Yu. Matrosova

I.  Levin

S. A. Ostanin

Self-checking Synchronous FSM Network Design with Low Overhead

Parag K. Lala

Guest Editorial

paper propos signal code cmos gate suitabl selfcheck circuit combin function block implement also next generat veri deep submicron technolog particular our function block satisfi strong faultsecur properti respect wide set possibl intern fault includ onli convent stuckat also transistor stuckon transistor stuckopen resist bridg delay crosstalk transient fault veri like affect next generat ics compar altern exist solut propos here doe impli ani critic constraint circuit electr paramet therefor suitabl adopt design veri deep submicron selfcheck circuit which compar today circuit present signific increas sensit paramet variat occur dure fabric

Cecilia  Metra

Michele  Favalli

Bruno  Riccò

Signal Coding and CMOS Gates for Combinational Functional Blocks of Very Deep Submicron Self-checking Circuits

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