In this paper new methods for the transformation of a given combinational circuit into
a self-dual circuit based on the notion of a self-dual complement are investigated. The
large variety of self-dual complements can be utilized to optimize the transformed self-dual
circuit. Self-dual duplication and self-dual parity prediction are considered in
detail. As a method for the reduction of self-dual outputs, output space compaction of
self-dual outputs is considered. For the first time we also describe in this paper how a
self-dual circuit can be modified into a self-dual fault-secure circuit.

A. Dmitriev

V. Saposhnikov

Vl. Saposhnikov

M. Goessel

Vl. Moshanin

A. Morosov

New Self-dual Circuits for Error Detection and Testing

This paper presents a novel method for designing Totally Self-Checking (TSC) m-out-of-n code checkers taking into account a realistic fault model including stuck-at,transistor stuck-on, transistor stuck-open, resistive bridging faults and breaks. Theproposed design method is the first method in the open literature that takes into accounta realistic fault model and can be applied for most practical values of m and n. Apartfrom the above the proposed checkers are very compact and very fast. The single outputcheckers are near optimal with respect to the number of transistors required fortheir implementation. Another benefit of the proposed TSC checkers is that all faultsare tested by a very small set of single pattern tests, thus the probability of achievingthe TSC goal is greater than in checkers requiring two-pattern tests. The single outputTSC checkers proposed in this paper are the first known single output TSC checkersfor m-out-of-n codes.

X.  Kavousianos

D.  Nikolos

G.  Sidiropoulos

Novel Single and Double Output TSC CMOS Checkers for m-out-of-n Codes

The design of integrated fault detector for on-line testing of linear analog systems isdiscussed in this paper. The method consists in a concurrent processing of available thenode voltage signals to provide a residual on-line, that carries information about thefaults. Contrary to the few previous works dealing with the particular case of statevariable analog systems, the method proposed here is useable without limitation fora larger class of linear analog systems, even when the state variables are not availableas measurable voltages. For this purpose, an algorithm providing an extended statespace model for any linear analog system from its netlist description is developedand implemented.

Emmanuel  Simeu

Optimal Detector Design for On-line Testing of Linear Analog Systems

A method of a self-checking synchronous Finite State Machine (FSM) network designwith low overhead is developed. Checkers are used only for FSMs, which output linesare at the same time output lines of the network. The checkers observe output lines ofthese FSMs. The method is based on reducing the problem to a self-checking synchronousFSM design. The latter is provided by applying a special description of FSMnamely, so-called unate Programmable Logic Array (PLAu) description. Single stuck-atfault on the FSM poles and gate poles are considered. PLAu realization of FSM allows afactorized or multilevel logic synthesis. They both provide a unidirectional manifestationof the above mentioned faults on the output lines of the corresponding FSMs. Thisrealization also gives rise to a transparency of each component FSM of the network forthe faults. PLAu realization is derived from the State Transition Graph (STG) descriptionof FSMs with using the m-out-of-n encoding of its states and insignificantexpanding the products of STG. The problem of replacing an arbitrary synchronousFSM network for the self-checking one with low overhead is discussed.

A. Yu. Matrosova

I.  Levin

S. A. Ostanin

Self-checking Synchronous FSM Network Design with Low Overhead

In this paper we propose signal coding and CMOS gates that are suitable to self-checkingcircuits with combinational functional blocks implemented also by next generation,very deep submicron technology. In particular, our functional blocks satisfythe Strongly Fault-Secure property with respect to a wide set of possible, internalfaults including not only conventional stuck-ats, but also transistor stuck-ons, transistorstuck-opens, resistive bridgings, delays, crosstalks and transient faults, that are verylikely to affect next generation ICs. Compared to alternative, existing solutions, thatproposed here does not imply any critical constraint on the circuit electrical parameters.Therefore, it is suitable to be adopted to design very deep submicron self-checking circuitswhich, compared to todays&#39; circuits, will present significantly increased sensitivityto parameter variations occurring during fabrication.

Cecilia  Metra

Michele  Favalli

Bruno  Ricc&#242;

Signal Coding and CMOS Gates for Combinational Functional Blocks of Very Deep Submicron Self-checking Circuits

Parag K. Lala

Guest Editorial

About this journal

Journal profile

Meet the editorial board

Editor spotlight

Submit your proposal

Do you think there is an emerging area of research that really needs to be highlighted? Or an existing research area that has been overlooked or would benefit from deeper investigation? Raise the profile of a research area by leading a Special Issue.

Special Issues

title

https://images.hindawi.com/journals/vlsi/vlsi.banner.jpg

facebook-domain-verification

twitter:card

twitter:site

twitter:title

twitter:url

twitter:image

VLSI Design | Hindawi

VLSI Design

This Issue is now open for submissions.
Papers are published upon acceptance, regardless of the Special Issue publication date.

Call for papers

Parag Lala