Although SRT division and square-root approaches and GST division approach havebeen known for long time, square-root architectures based on the GST approach havenot been proposed so far which do not require a final division/multiplication of the scalefactor. A GST square-root architecture is developed without requiring either amultiplication to update the scaled square-root quotient in each iteration or a division/multiplication by the scaling factor after completing the square-root iterations.Additionally, quantitative comparison of speed and power consumption of GST andSRT division/square-root units are presented. Shared divider and square-root units aredesigned based on the SRT and the GST approaches, in minimally and maximallyredundant radix-4 representations. Simulations demonstrate that the worst-case overalllatency of the minimally-redundant GST architecture is 35&#37; smaller compared to theSRT. Alternatively, for a fixed latency, the minimally-redundant GST architecturebased division and square-root operations consume 32&#37; and 28&#37; less power,respectively, compared to the maximally-redundant SRT approach.

Martin  Kuhlmann

Keshab K. Parhi

A Novel Low-power Shared Division and Square-root Architecture Using the GST Algorithm

Recent trends in IC technology have given rise to a new requirement, that of low powerdissipation during testing, that Built-In Self-Test (BIST) structures must target alongwith the traditional requirements. To this end, by exploiting the inherent properties ofCarry Save, Carry Propagate and modified Booth multipliers, in this paper we proposenew power-efficient BIST structures for them. The proposed BIST schemes are derivedby: (a) properly assigning the Test Pattern Generator (TPG) outputs to the multiplierinputs, (b) modifying the TPG circuits and (c) reducing the test set length. Our resultsindicate that the total power dissipated during testing can be reduced from 29.3&#37; to54.9&#37;, while the average power per test vector applied can be reduced from 5.8&#37; to36.5&#37; and the peak power dissipation can be reduced from 15.5&#37; to 50.2&#37; dependingon the implementation of the basic cells and the size of the multiplier. The testapplication time is also significantly reduced, while the introduced BIST schemesimplementation area is small.

D.  Bakalist

X.  Kavousianos

H. T. Vergos

D.  Nikolos

G. Ph. Alexiou

Low Power Built-In Self-Test Schemes for Array and Booth Multipliers

A second-order gm-C filter based on the Floating-Gate MOS (FGMOS) technique is presented. It uses a new fully differential transconductor and works at 2 V of voltage
supply with a full differential input linear range and a THD below 1%. Programming
and tuning are performed by means of a single voltage signal. The transconductor incorporates
a novel Common-Mode Feedback Circuit (CMFB) based also on FGMOS
transistors.

Esther O. Rodríguez-Villegas

Alberto Yúfera

Adoración Rueda

A Low-Voltage Floating-Gate MOS Biquad

Current mobile phone applications demand high performance from the DSP, and future
generations are likely to require even greater throughput. However, it is important to
balance these processing demands against the requirement of low power consumption
for extended battery lifetime. A novel low-power digital signal processor (DSP)
architecture CADRE (Configurable Asynchronous DSP for Reduced Energy) addresses
these requirements through a multi-level power reduction strategy. A parallel architecture
and configurable compressed instruction set meets the throughput requirements
without excessive program memory bandwidth, while a large register file reduces the
cost of data accesses. Sign-magnitude representation is used for data, to reduce switching
activity within the datapath. Asynchronous design gives fine-grained activity control
without the complexities of clock gating, and gives low electromagnetic interference.
Finally, the operational model of the target application allows for a reduced interrupt
structure, simplifying processor design by avoiding the need for exact exceptions.

Mike Lewis

Linda Brackenbury

CADRE: A Low-power, Low-EMI DSP Architecture for Digital Mobile Phones

We present more evidence in a 0.25 &#956;m CMOS technology that the pass-transistor logic(PTL) structure that mixes conventional PTL structure with static logic gates canachieve better performance and lower power consumption compared to conventionalPTL structure. The goal is to use the static gates to perform both logic functions as wellas buffering. Our experimental results demonstrate that the proposed mixed PTLstructure beats pure static structure and conventional PTL in 9 out of 15 test cases foreither delay or power consumption or both in a 0.25 &#956;m CMOS process. The averagedelay, power consumption, and power-delay product of the proposed structure for 15test cases are 10&#37; to 20&#37; better of than the pure static implementations and up to 50&#37;better than the conventional PTL implementations.

Geun Rae Cho

Tom  Chen

On Mixed PTL/Static Logic for Low-power and High-speed Circuits

A semicustom ASIC design methodology is used to develop a low power DSP core formobile (battery powered) applications. Different low power design techniques are used,including dual voltage, low power library elements, accurate power reporting, pseudomicrocode,transition-once logic, clock gating, and others.

Alvar  Dean

David  Garrett

Mircea R. Stan

Sebastian  Ventrone

Low Power Design for ASIC Cores

Strategies for the design of ultra low power multipliers and multiplier-accumulators
are reported. These are optimized for asynchronous applications being able to take
advantage of data-dependent computation times. Nevertheless, the low power
consumption can be obtained in both synchronous and asynchronous environments.
Central to the energy efficiency is a dynamic-logic technique termed Conditional
Evaluation which is able to exploit redundancies within the carry-save array and deliver
energy consumption which is also heavily data-dependent.Energy efficient adaptations for handling two's complement operands are introduced.
Area overheads of the proposed designs are estimated and transistor level simulation
results of signed and unsigned multipliers as well as a signed multiplier-accumulator are given.Normalized comparisons with other designs show our approach to use less energy
than other published multipliers.

V. A. Bartlett

E. Grass

Exploiting Data-dependencies in Ultra Low-power DSP Arithmetic

In this paper, a new low power design method of the FIR filter for image processing isproposed. Because the correlation between adjacent pixels is very high in image data,the clock gating technique can be a good candidate for low power strategy. However,the conventional clock gating strategy that is applied independently to every flip-flopof the filter give rise to too much additional area overhead and couldn&#39;t get a good resultin the power reduction. In our method, each tap register, which is used to delay theinput data in the filter, is partitioned into two sub-registers according to the correlationcharacteristic of its input space. For the sub-register which highly correlated data isinputted into, the dynamic power consumption is reduced by diminishing switchingactivity of the clock signal. We can also reduce the additional hardware overhead bypropagating the clock gating control signal of the first tap register to other tap registers.To identify the efficiency of the proposed design method, we perform the experiments onsome filters that are designed in VHDL. The power estimation tool says that theproposed method can reduce the power dissipation of the filter by more than 18&#37;compared to the conventional filter design methods.

Jun Mo Jung

Jong-Wha  Chong

A Low Power FIR Filter Design for Image Processing

The increasing prominence of wireless multimedia systems and the need to limit powercapability in very-high density VLSI chips have led to rapid and innovativedevelopments in low-power design. Power reduction has emerged as a significantdesign constraint in VLSI design. The need for wireless multimedia systems leads tomuch higher power consumption than traditional portable applications. This paperpresents possible optimization technique to reduce the energy consumption for wirelessmultimedia communication systems. Four topics are presented in the wirelesscommunication systems subsection which deal with architectures such as PNacquisition, parallel correlator, matched filter and channel coding. Two topics includethe IDCT and motion estimation in multimedia application.These topics consider algorithms and architectures for low power design such as usinghybrid architecture in PN acquisition, analyzing the algorithm and optimizing thesample storage in parallel correlator, using complex matched filter that analogoperational circuits controlled by digital signals, adopting bit serial arithmetic for theACS operation in viterbi decoder, using CRC to adaptively terminate the SOVAiteration in turbo decoder, using codesign in RS codec, disabling the processingelements as soon as the distortion values become great than the minimum distortionvalue in motion estimation, and exploiting the relative occurrence of zero-valued DCTcoefficient in IDCT.

Koon-Shik  Cho

Jun-Dong  Cho

Low Power Digital Multimedia Telecommunication Designs

A highly regular parallel multiplier architecture along with the novel low-power, high-performanceCMOS implementation circuits is presented. The superiority is achievedthrough utilizing a unique scheme for recursive decomposition of partial productmatrices and a recently proposed non-binary arithmetic logic as well as thecomplementary shift switch logic circuits.The proposed 64&#215;64-b parallel multiplier possesses the following distinct features:(1) generating 64 8&#215;8-b partial product matrices instead of a single large one; (2)comprising only four stages of bit reductions: first, by 8&#215;8-b small parallel multipliers,then, by small parallel counters in each of the remaining three stages. A family of shiftswitch parallel counters, including non-binary (6, 3)&#8727; and complementary (k, 2) for2 &#8804; k &#8804; 8, are proposed for the efficient bit reductions; (3) using a simple final adder.The non-binary logic operates 4-bit state signals (representing integers ranging from(0 to 3), where no more than half of the signal bits are subject to value-change at anylogic stage. This and others including minimum transistor counts, fewer inverters, andlow-leakage logic structure, significantly reduce circuit power dissipation.

Rong  Lin

A Regularly Structured Parallel Multiplier with Low-power Non-binary-logic Counter Circuits

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