VLSI Design

Physical Design Automation in Deep Submicron


Status
Published

Guest Editors
Jun-Dong Cho

Physical Design Automation in Deep Submicron

Articles

  • Special Issue
  • - Volume 10
  • - Article ID 081698

Accurate Interconnection Length Estimations for Predictions Early in the Design Cycle

Dirk Stroobandt | Jan Van Campenhout
  • Special Issue
  • - Volume 10
  • - Article ID 047230

Lower-Power and Min-Crosstalk Channel Routing for Deep-Submicron Layout Design

S. H. Nam | J. D. Cho | D. Wagner
  • Special Issue
  • - Volume 10
  • - Article ID 035313

Preface

Jun-Dong Cho
  • Special Issue
  • - Volume 10
  • - Article ID 089835

Empirical Study of Block Placement by Cluster Refinement

Jin Xu | Pei-Ning Guo | Chung-Kuan Cheng
  • Special Issue
  • - Volume 10
  • - Article ID 038974

Tuning Strategies for Global Interconnects in High-Performance Deep-Submicron ICs

Andrew B. Kahng | Sudhakar Muddu | Egino Sarto
  • Special Issue
  • - Volume 10
  • - Article ID 050892

Hierarchy Restructuring for Hierarchical LVS Comparison

Wonjong Kim | Hyunchul Shin
  • Special Issue
  • - Volume 10
  • - Article ID 085272

Logic Synthesis for a Regular Layout

Malgorzata Chrzanowska-Jeske | Yang Xu | Marek Perkowski
  • Special Issue
  • - Volume 10
  • - Article ID 042648

Placement with Incomplete Data

Maogang Wang | Prithviraj Banerjee | Majid Sarrafzadeh
  • Special Issue
  • - Volume 10
  • - Article ID 093607

Analytical Engines are Unnecessary in Top-down Partitioning-based Placement

C. J. Alpert | A. E. Caldwell | ... | M. S. Moroz