In this paper we propose an efficient cluster refinement approach for macro-cell placement.
The algorithm selects a cluster of blocks dynamically, and finds an optimal solution
for all the blocks in the cluster simultaneously. This is different from previous zone refinement
approach which optimizes the allocation of one single block in each operation.
Experimental results on the MCNC benchmark circuits show that the approach achieves
excellent area utilization while minimizing the wire length at the same time.

Jin Xu

Pei-Ning Guo

Chung-Kuan Cheng

Empirical Study of Block Placement by Cluster Refinement

Consider a set of nets given by horizontal segments <mml:math id="E1" xmlns:mml="http://www.w3.org/1998/Math/MathML"><mml:mrow><mml:mi>S</mml:mi><mml:mtext> </mml:mtext><mml:mo>=</mml:mo><mml:mtext> </mml:mtext><mml:mo>{</mml:mo><mml:msub><mml:mi>s</mml:mi><mml:mn>1</mml:mn></mml:msub><mml:mo>,</mml:mo><mml:mtext> </mml:mtext><mml:msub><mml:mi>s</mml:mi><mml:mn>2</mml:mn></mml:msub><mml:mo>,</mml:mo><mml:mtext> </mml:mtext><mml:mn>...</mml:mn><mml:mo>,</mml:mo><mml:mtext> </mml:mtext><mml:msub><mml:mi>s</mml:mi><mml:mi>n</mml:mi></mml:msub><mml:mo>}</mml:mo></mml:mrow></mml:math> and a set of tracks <mml:math id="E2" xmlns:mml="http://www.w3.org/1998/Math/MathML"><mml:mrow><mml:mi>T</mml:mi><mml:mtext> </mml:mtext><mml:mo>=</mml:mo><mml:mo>{</mml:mo><mml:msub><mml:mi>t</mml:mi><mml:mn>1</mml:mn></mml:msub><mml:mo>,</mml:mo><mml:msub><mml:mi>t</mml:mi><mml:mn>2</mml:mn></mml:msub><mml:mo>,</mml:mo><mml:mn>...</mml:mn><mml:mo>,</mml:mo><mml:msub><mml:mi>t</mml:mi><mml:mi>k</mml:mi></mml:msub><mml:mo>}</mml:mo></mml:mrow></mml:math> in a channel, then a track assignment consists in an assignment
of the nets to the tracks such that no two nets assigned to the same track overlap. One
important goal is to find a track assignment with the minimum number of tracks such
that the signal interference between nets assigned to neighboring tracks is minimized.
This problem is called crosstalk minimization. For a given track assignment with k
tracks, crosstalk can be reduced by finding another track assignment for S with k tracks (i.e., by permuting tracks). However, considering all possible permutations requires
exponential time. For general cost function for crosstalk measure, the problem is NPhard.
Several heuristic approaches were previously presented. In this paper, we consider
special instances of the crosstalk-minimization problem where the cost function depends
only on the length of the segments that runs in parallel and all pairs of segments intersect.
An algorithm solving this problem in O(n log n) time is presented. An extension
applied to the instances with more general function of switching activity and mixed
signal sensitivity to reduce crosstalk and power consumption is also presented.

S. H. Nam

J. D. Cho

D. Wagner

Lower-Power and Min-Crosstalk Channel Routing for Deep-Submicron Layout Design

Important layout properties of electronic circuits include space requirements and
interconnection lengths. In the process of designing these circuits, a reliable pre-layout
interconnection length estimation is essential for improving placement and routing
techniques. Donath found an upper bound for the average interconnection length that
follows the trends of experimentally observed average lengths. Yet, this upper bound
deviates from the experimental value by a factor <mml:math id="E1" xmlns:mml="http://www.w3.org/1998/Math/MathML"><mml:mrow><mml:mi>δ</mml:mi><mml:mtext> </mml:mtext><mml:mo>≈</mml:mo><mml:mtext> </mml:mtext><mml:mn>2</mml:mn></mml:mrow></mml:math>, which is not sufficiently accurate
for some applications. We show that we obtain a significantly more accurate estimate by
taking into account the inherent features of the optimal placement process.

Dirk Stroobandt

Jan  Van Campenhout

Accurate Interconnection Length Estimations for Predictions Early in the Design Cycle

Jun-Dong Cho

Preface

Interconnect tuning is an increasingly critical degree of freedom in the physical design ofhigh-performance VLSI systems. By interconnect tuning, we refer to the selection of linethicknesses, widths and spacings in multi-layer interconnect to simultaneously optimizesignal distribution, signal performance, signal integrity, and interconnect manufacturabilityand reliability. This is a key activity in most leading-edge design projects, but hasreceived little attention in the literature. Our work provides the first technology-specificstudies of interconnect tuning in the literature. We center on global wiring layers andinterconnect tuning issues related to bus routing, repeater insertion, and choice ofshielding/spacing rules for signal integrity and performance. We address four basicquestions. (1) How should width and spacing be allocated to maximize performance fora given line pitch&#63; (2) For a given line pitch, what criteria affect the optimal interval atwhich repeaters Should be inserted into global interconnects&#63; (3) Under what circumstancesare shield wires the optimum technique for improving interconnect performance&#63;(4) In global interconnect with repeaters, what other interconnect tuning is possible&#63;Our study of question (4) demonstrates a new approach of offsetting repeater placementsthat can reduce worst-case cross-chip delays by over 30&#37; in current technologies.

Andrew B. Kahng

Sudhakar  Muddu

Egino  Sarto

Tuning Strategies for Global Interconnectsin High-Performance Deep-Submicron ICs

A new hierarchical layout vs. schematic (LVS) comparison system for layout verification
has been developed. The schematic hierarchy is restructured to remove ambiguities for
consistent hierarchical matching. Then the circuit hierarchy is reconstructed from the
layout netlist by using a modified SubGemini algorithm recursively in bottom-up fashion.
For efficiency, simple gates are found by using a fast rule-based pattern matching
algorithm during preprocessing. Experimental results show that our hierarchical netlist
comparison technique is effective and efficient in CPU time and in memory usage,
especially when the circuit is large and hierarchically structured.

Wonjong Kim

Hyunchul Shin

Hierarchy Restructuring for Hierarchical LVS Comparison

New algorithms for generating a regular two-dimensional layout representation formulti-output, incompletely specified Boolean functions, called, Pseudo-Symmetric BinaryDecision Diagrams (PSBDDs), are presented. The regular structure of the functionrepresentation allows accurate prediction of post-layout areas and delays before thelayout is physically generated. It simplifies power estimation on the gate level and allowsfor more accurate power optimization. The theoretical background of the new diagrams,which are based on ideas from contact networks, and the form of decision diagramsfor symmetric functions is discussed. PSBDDs are especially well suited for deepsub-micron technologies where the delay of interconnections limits the device performance.Our experimental results are very good and show that symmetrization of reallifebenchmark functions can be done efficiently.

Malgorzata  Chrzanowska-Jeske

Yang  Xu

Marek  Perkowski

Logic Synthesis for a Regular Layout

Traditional placement problems are studied under a fully specified cell library and acomplete netlist. However, in the first, e.g., 2 years of a 2 &#8211; 3 year microprocessor designcycle, the detailed netlist is unavailable. For area and performance estimation, layoutmust nevertheless be done with incomplete information. Another source of incompletenesscomes from logic synthesis changes; some instances and their parameters will changeas the project evolves. In the re-configurable computing area, sometimes we need toperform quick placement before all information is available. The problem of placementwith incomplete data (PID) can be abstracted as having to place a circuit when <mml:math xmlns:mml="http://www.w3.org/1998/Math/MathML"><mml:mrow><mml:msub><mml:mi>p</mml:mi><mml:mi>c</mml:mi></mml:msub><mml:mi>&#x0025;</mml:mi></mml:mrow></mml:math> of the cells and <mml:math xmlns:mml="http://www.w3.org/1998/Math/MathML"><mml:mrow><mml:msub><mml:mi>p</mml:mi><mml:mi>n</mml:mi></mml:msub><mml:mi>&#x0025;</mml:mi></mml:mrow></mml:math> of the nets are missing. The key challenge in PID is how to add missingcells and nets.In this paper, two &#8220;patching-methods&#8221; for adding missing nets and cells are proposed.The methods are called abstraction and fusion.Experimental results are very interesting. First, they show that PID is a difficult problemand an arbitrary (and perhaps intuitively sound) method may not produce highqualityresults. Experiments verify that the abstraction method is a very good predictorand that fusion is not. Specifically, when a circuit has 10&#37; incompleteness, abstractioncan predict the final total wirelength with an error of 5.8&#37; while fusion has a 67.8&#37; errorin predicting the wirelength in the same circuit.

Maogang  Wang

Prithviraj  Banerjee

Majid  Sarrafzadeh

Placement with Incomplete Data

The top-down &#8220;quadratic placement&#8221; methodology is rooted in such works as [36, 9, 32]and is reputedly the basis of commercial and in-house VLSI placement tools. Thismethodology iterates between two basic steps: solving sparse systems of linear equationsto achieve a continuous placement solution, and &#8220;legalization&#8221; of the placement bytransportation or partitioning. Our work, which extends [5], studies implementationchoices and underlying motivations for the quadratic placement methodology. We firstrecall some observations from [5], e.g., that (i) Krylov subspace engines for solvingsparse linear systems are more effective than traditional successive over-relaxation(SOR) engines [33] and (ii) that correlation convergence criteria can maintain solutionquality while using substantially fewer solver iterations. The focus of our investigation isthe coupling of numerical solvers to iterative partitioners that is a hallmark of thequadratic placement methodology. We provide evidence that this coupling may havehistorically been motivated by the pre-1990’s weakness of min-cut partitioners, i.e.,numerical engines were needed to provide helpful hints to weak min-cut partitioners. Inparticular, we show that a modern multilevel FM implementation [2] derives no benefitfrom such coupling. We also show that most insights obtained from study of individualmin-cut partitioning instances (within the top-down placement) also hold within theoverall context of a complete top-down placer implementation.

C. J. Alpert

A. E. Caldwell

T. F. Chan

D. J.-H. Huang

A. B. Kahng

I. L. Markov

M. S. Moroz

Analytical Engines are Unnecessary in Top-down Partitioning-based Placement

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