VLSI Design

VLSI Testing


Status
Published

Guest Editors
Sunil Das

VLSI Testing

Articles

  • Special Issue
  • - Volume 12
  • - Article ID 028741

Defect Level Estimation for Pseudorandom Testing Using Stochastic Analysis

W. B. Jone | D. C. Huang | ... | S. R. Das
  • Special Issue
  • - Volume 12
  • - Article ID 045324

An Efficient Test Pattern Generation Scheme for an On Chip BIST

B. K. S. V. L. Varaprasad | L. M. Patnaik | ... | V. K. Agrawal
  • Special Issue
  • - Volume 12
  • - Article ID 071565

Guest Editorial

Sunil R. Das
  • Special Issue
  • - Volume 12
  • - Article ID 032515

BIST-Based Fault Diagnosis in the Presence of Embedded Memories

Jacob Savir
  • Special Issue
  • - Volume 12
  • - Article ID 083474

A Fine Grain Configurable Logic Block for Self-checking FPGAs

P. K. Lala | A. Walker
  • Special Issue
  • - Volume 12
  • - Article ID 091710

BIST Analysis of an Embedded Memory Associated Logic

Jacob Savir
  • Special Issue
  • - Volume 12
  • - Article ID 075139

Efficient Test Application for Core-Based Systems Using Twisted-Ring Counters

Anshuman Chandra | Krishnendu Chakrabarty | Mark C. Hansen
  • Special Issue
  • - Volume 12
  • - Article ID 087048

Random Pattern Testability Enhancement by Circuit Rewiring

Shih-Chieh Chang | Kwen-Yo Chen | ... | Sunil R. Das
  • Special Issue
  • - Volume 12
  • - Article ID 037087

Test Generators Need to be Modified to Handle CMOS Designs

Jacob Savir
  • Special Issue
  • - Volume 12
  • - Article ID 079703

Effect of Reverse Body Bias on Current Testing of 0.18 μm Gates

Xiaomei Liu | Prachi Sathe | Samiha Mourad

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