Generally, there exist random-pattern resistant faults that result in the poor fault
coverage in Build-In Self-Testing (BIST) scheme. In this paper, we propose a method to
enhance the random pattern testability by a circuit restructuring technique, called circuit
rewiring. The basic idea of rewiring is to replace a wire by another wire with the circuit
functionality remaining unchanged. For two types of rewiring, fanin rewiring and
fanout rewiring, we first analyze the testability change for each type of wire replacement.
Based on the analysis, an efficient algorithm is given to enhance circuit testability. For a
poor observability node, we try to increase its observability by adding an additional
fanout to the node and removing an alternative wire whose source node has relatively
good observability. The technique does not introduce any hardware overhead and
performance degradation since a wire addition is followed immediately by another wire
removal. Thus, it is basically cost-free when compared to other testability enhancement
techniques.

Shih-Chieh Chang

Kwen-Yo Chen

Ching-Hwa Cheng

Wen-Ben Jone

Sunil R. Das

Random Pattern Testability Enhancement by Circuit Rewiring

We present novel test set encoding and pattern decompression methods for core-basedsystems. These are based on the use of twisted-ring counters and offer a number ofimportant advantages&#8211;significant test compression (over 10X in many cases), less testermemory and reduced testing time, the ability to use a slow tester without compromisingtest quality or testing time, and no performance degradation for the core under test.Surprisingly, the encoded test sets obtained from partially-specified test sets (test cubes)are often smaller than the compacted test sets generated by automatic test patterngeneration programs. Moreover, a large number of patterns are applied test-per-clock tocores, thereby increasing the likelihood of detecting non-modeled faults. Experimentalresults for the ISCAS benchmark circuits demonstrate that the proposed testarchitecture offers an attractive solution to the problem of achieving high test qualityand low testing time with relatively slower, less expensive testers.

Anshuman  Chandra

Krishnendu  Chakrabarty

Mark C. Hansen

Efficient Test Application for Core-Based Systems Using Twisted-Ring Counters

Guest Editorial

Of late some interesting and useful work has been done on the problem of testing logicsurrounding embedded memories. This work assumes that the logic surrounding thememory is functionally partitioned and that the different partitions are logically isolatedone from the other.This paper expands upon past work using a more flexible design rule which allowsfeed-forward connections between the data-path Prelogic and Postlogic. The connectionsare such that there is no feedback from the memory outputs to its inputs, and boththe Prelogic and the Postlogic are disconnected from the Address and Control logic.Under this design rule we show the auxiliary circuits used to determine the randompattern testability of faults in the circuitry driving the address inputs and the controls ofthe two-port memory.The techniques described herein are intended to be used in conjunction with the cuttingalgorithm for testability measurement in built-in self-test (BIST) designs [2, 11, 17], butmay also be suitable for use with other detection probability tools [9, 19], and simulationtools [20].

Jacob  Savir

BIST Analysis of an Embedded Memory Associated Logic

Systematic investigations on defect-free IDDQ in deep submicron CMOS with reversebody bias were performed by SPICE simulation towards an attempt to improveresolution of IDDQ measurement. Effects of reverse body bias on off-state leakage ofscaled CMOS devices and IDDQ of typical CMOS circuit cells were investigated. It wasfound that reverse body bias can effectively reduce defect-free IDDQ of typical 0.18 &#956;mtechnology devices and logic gates while the faulty current is not as much reduced. Thereduction in defect-free IDDQ was enhanced as the device temperature went up anddiminishes as the temperature went down. Further investigation showed that reversebody bias also makes the defect-free IDDQ less sensitive to the input state; therefore, asingle IDDQ current threshold might still be used for IDDQ testing of 0.18 &#956;m CMOS circuits. It was found that there might exist an optimal reverse body bias that minimizedthe defect-free IDDQ current. The optimal reverse bias value decreases as the temperaturewent down and might vary from circuit to circuit, process to process, andtechnology generation to generation.

Xiaomei  Liu

Prachi  Sathe

Samiha  Mourad

Effect of Reverse Body Bias on Current Testing of 0.18 &#956;m Gates

This paper proposes a logic cell that can be used as a building block for Self-checking
FPGAs. The proposed logic cell consists of two 2-to-1 multiplexers, three 4-to-1
multiplexers and a D flip-flop. The cell has been designed using Differential Cascode
Voltage Switch Logic. It is self-checking for all single transistor stuck-on and stuck-off
faults as well as stuck-at faults at the inputs of each multiplexers and the D flip-flop. The
multiplexers and the D flip-flop provide either correct (complementary) output in the
absence of above-mentioned faults; otherwise the outputs are identical.

P. K. Lala

A. Walker

A Fine Grain Configurable Logic Block for Self-checking FPGAs

An efficient method is described for using fault simulation as a solution to the diagnosticproblem created by the presence of embedded memories in BIST designs. Thesimulation is event-table-driven. Special techniques are described to cope with the faultsin the Prelogic, Postlogic, and the logic embedding the memory control or addressinputs. It is presumed that the memory itself has been previously tested, using automatictest pattern generation (ATPG) techniques via the correspondence inputs, and has beenfound to be fault-free.

BIST-Based Fault Diagnosis in the Presence of Embedded Memories

Testing and power consumption are becoming two critical issues in VLSI design due to
the growing complexity of VLSI circuits and remarkable success and growth of low
power applications (viz. portable consumer electronics and space applications). On chip
Built In Self Test (BIST) is a cost-effective test methodology for highly complex VLSI
devices like Systems On Chip. This paper deals with cost-effective Test Pattern Generation
(TPG) schemes in BIST. We present a novel methodology based on the use of
a suitable Linear Feedback Shift Register (LFSR) which cycles through the required
sequences (test vectors) aiming at a desired fault coverage causing minimum circuit
toggling and hence low power consumption while testing. The proposed technique uses
circuit simulation data for modeling. We show how to identify the LFSR using graph
theory techniques and compute its feedback coefficients (i.e., its characteristic
polynomial) for realization of a Test Pattern Generator.

B. K. S. V. L. Varaprasad

L. M. Patnaik

H. S. Jamadagni

V. K. Agrawal

An Efficient Test Pattern Generation Scheme for an On Chip BIST

CMOS designs have some unique properties that prevent existing test generators fromcomputing a test vector for a fault when one might exist. The problem lies in thepremises laid out on what it takes to detect a stuck-at fault. The basic premise that statesthat it is required to set a line to 0(1) in order to detect a stuck-at 1(0) fault, and thenpropagate the error to an observable point, needs to be re-examined. This is due to theexistence of indeterminate states throughout the logic. The paper distinguishes betweenthe traditional test vector (here called a hard-detect), and a potential test vector (herecalled a soft-detect). Our proposed test set is the union of hard and soft-detects. We alsore-examine the issue of redundancy and show that it needs to be re-defined in order tocomply with CMOS technology behavior.This paper shows several examples to illustrate the problem; describes what it takes inorder to remedy it; proposes possible enhancements to existing test generationalgorithms, and outlines the risks faced in the event that no correcting steps are taken.

Test Generators Need to be Modified to Handle CMOS Designs

Pseudorandom testing has been widely used in built-in self-testing of VLSI circuits.Although the defect level estimation for pseudorandom testing has been performedusing sequential statical analysis, no closed form can be accomplished as complexcombinatorial enumerations are involved. In this work, a Markov model is employed todescribe the pseudorandom test behaviors. For the first time, a closed form of the defectlevel equation is derived by solving the differential equation extracted from the Markovmodel. The defect level equation clearly describes the relationships among defect level,fabrication yield, the number of all input combinations, circuit detectability (in terms ofthe worst single stuck-at fault), and pseudorandom test length. The Markov model isthen extended to consider all single stuck-at faults, instead of only the worst singlestuck-at fault. Results demonstrate that the defect level analysis for pseudorandomtesting by only dealing with the worst single stuck-at fault is not adequate (In fact, theworst single stuck-at fault analysis is just a special case). A closed form of the defectlevel equation is successfully derived to incorporate all single stuck-at faults intoconsideration. Although our discussions are primarily based on the single struck-at faultmodel, it is not difficult to extend the results to other fault types.

W. B. Jone

D. C. Huang

S. C. Chang

S. R. Das

Defect Level Estimation for Pseudorandom Testing Using Stochastic Analysis

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Articles

Random Pattern Testability Enhancement by Circuit Rewiring

Efficient Test Application for Core-Based Systems Using Twisted-Ring Counters

Guest Editorial

BIST Analysis of an Embedded Memory Associated Logic

Effect of Reverse Body Bias on Current Testing of 0.18 μm Gates

A Fine Grain Configurable Logic Block for Self-checking FPGAs

BIST-Based Fault Diagnosis in the Presence of Embedded Memories

An Efficient Test Pattern Generation Scheme for an On Chip BIST

Test Generators Need to be Modified to Handle CMOS Designs

Defect Level Estimation for Pseudorandom Testing Using Stochastic Analysis