A new approach for power analysis of microprocessors has recently been proposed &#91;14&#93;.The idea is to look at the power consumption in a microprocessor from the point of viewof the actual software executing on the processor. The basic component of this approachis a measurement based, instruction-level power analysis technique. The techniqueallows for the development of an instruction-level power model for the given processor,which can be used to evaluate software in terms of the power consumption, and forexploring the optimization of software for lower power. This paper describes theapplication of this technique for a comprehensive instruction-level power analysis of acommercial 32-bit RISC-based embedded microcontroller. The salient results of theanalysis and the basic instruction-level power model are described. Interestingobservations and insights based on the results are also presented. Such aninstruction-level power analysis can provide cues as to what optimizations in themicro-architecture design of the processor would lead to the most effective powersavings in actual software applications. Wherever the results indicate such optimizations,they have been discussed. Furthermore, ideas for low power software design, assuggested by the results, are described in this paper as well.

Vivek  Tiwari

Mike Tien-Chien Lee

Power Analysis of a 32-bit Embedded Microcontroller

High level synthesis is the process of generating register transfer (RT) level designs from
behavioral specifications. High level synthesis systems have traditionally taken into
account such constraints as area, clock period and throughput time. Many high level
synthesis systems [1] permit generation of many alternative RT level designs meeting
these constraints in a relatively short time. If it is possible to accurately estimate the
power consumption of RT level designs, then a low power design from among these
alternatives can be selected.In this paper, we present an accurate power estimation technique for register transfer
level designs generated by high level synthesis systems. The technique has four main
aspects: (1) Each RT level component used in high level synthesis is characterized for
average switched capacitance per input vector. This data is stored in the RT level
component library. (2) Using user-specified stimuli, the given behavioral description is
simulated and event activities of various operators and carriers are measured. Then, the
behavioral specification is submitted to the synthesis system and a number of alternative
RTL designs meeting speed, space and throughput rate constraints are generated. (3)
Event activity of each component in an RT level design is estimated using the event
activities measured at the time of behavior level profiling and the structure of the RTL
design itself. (4) The event activities so obtained are then used to modulate the average
switched capacitances of the respective RT level components to obtain an estimate the
total switched capacitance of each component.Detailed power estimation procedures for the three different parts of RTL designs,
namely, data path, controller and interconnect are presented. Experimental results
obtained from a variety of designs show that the power estimates are within 3%–10%
of the actual power measured by simulating the transistor level designs extracted from
mask layouts.

Srinivas Katkoori

Ranga Vemuri

Architectural Power Estimation Based on Behavior Level Profiling

Optimizing energy during the synthesis of VLSI systems for realtime-constrainedembedded applications is an important new problem. This paper presents a newmethodology for simultaneous scheduling and allocation of VLSI systems whichminimize estimated energy for large realtime compute intensive applications.Minimization of estimated energy and VLSI chip area using hierarchical decomposition,bin packing algorithms and integer linear programming techniques along with voltagescaling is performed. Common subexpression elimination, precomputation, dataregeneration, and loop merging transformations are supported. A large complex realindustrial application, audio compression, donated by Motorola, is used to study theenergy savings using different single and multichip system implementations. Results ofsynthesizing this complex application show that up to 10 times improvement inestimated energy are attainable for only 2.7 times increase in estimated chip area.Precomputation and other low energy transformations provided on average over 1.6times savings in energy respectively. This research is important for industry since energydissipation consideration at the early stages of design is crucial for mapping highperformance applications into cost-efficient and reliable systems.

Catherine H. Gebotys

Optimizing Energy During Systems Synthesis of Computer Intensive Realtime Applications

Higher levels of integration have led to a generation of integrated circuits for which
power dissipation and reliability are major design concerns. In CMOS circuits, both of
these problems are directly related to the extent of circuit switching activity. The average
number of transitions per second at a circuit node is a measure of switching activity that
has been called the transition density. This paper presents a statistical simulation
technique to estimate individual node transition densities in combinational logic
circuits. The strength of this approach is that the desired accuracy and confidence can be
specified up-front by the user. Another key feature is the classification of nodes into two
categories: regular- and low-density nodes. Regular-density nodes are certified with
user-specified percentage error and confidence levels. Low-density nodes are certified
with an absolute error, with the same confidence. This speeds convergence while
sacrificing percentage accuracy only on nodes which contribute little to power
dissipation and have few reliability problems.

Farid N. Najm

Michael G. Xakellis

Statistical Estimation of the ,Switching Activity in VLSI Circuits

Gary  Yeap

Guest Editorial

We propose a logic synthesis system that includes power optimization after technology
mapping. Our approach is unique in that our post-mapping logic transformations take
into account information on circuit delay, capacitance, arrival times, glitches, etc., to
provide much better accuracy than previously proposed technology-independent power
optimization methods. By changing connections in a mapped circuit, we achieve power
improvements up to 13% in case of area- or delay-optimized circuits, with reductions
also in area and delay. We show that by applying the proposed technique on circuits
that are already restructured for lower switching activity using the technique presented
in [11], total power savings up to 59% in case of area-optimized circuits and 38% in case
of delay-optimized circuits are achievable. The post-mapping transformations are based
on the transition density model of circuit switching activity and the concept of
permissible logic functions. The techniques presented here are applicable equally well to
both synchronous and asynchronous circuits. The power measurements are done under
a general delay model.

Rajendran Panda

Post-Mapping Transformations for Low-Power Synthesis

Sleep mode operation and exploiting it to minimize the average power consumption are
of great importance in modern VLSI circuits. In general, sleep mode refers to the mode
in which part(s) of the system are idle. In this paper, we study the problem of
partitioning a circuit according to the activity patterns of its elements such that circuit
elements with similar activity patterns are packed into the same partition. Then a
partition can be placed in sleep mode during the time intervals all elements contained in
that partition are idle. We formulate the partitioning problem to exploit sleep mode
operation and show that the problem is NP-complete. We present polynomial time
algorithms for practical classes of the problem. Applications of the problem to memory
and module partitioning and clock gating are discussed. The experimental data confirm
that a careful partitioning allows upto 40% more sleep time which could be exploited to
minimize the average power consumption.

Amir H. Farrahi

Gustavo E. Téllez

Majid Sarrafzadeh

Exploiting Sleep Mode for Memory Partitioning and Other Applications

About this journal

Journal profile

Meet the editorial board

Editor spotlight

Submit your proposal

Do you think there is an emerging area of research that really needs to be highlighted? Or an existing research area that has been overlooked or would benefit from deeper investigation? Raise the profile of a research area by leading a Special Issue.

Special Issues

title

https://images.hindawi.com/journals/vlsi/vlsi.banner.jpg

twitter:card

twitter:site

twitter:title

twitter:url

twitter:image

VLSI Design | Hindawi

VLSI Design

This Issue is now open for submissions.
Papers are published upon acceptance, regardless of the Special Issue publication date.