Table of Contents

New Algorithmic Techniques for Complex EDA Problems

Call for Papers

Original papers are invited for a special issue of the VLSI Design journal on “New Algorithmic Techniques in EDA”. There are two broad sets of effects that result from the rapidly decreasing feature sizes in CMOS VLSI (ASICs, SoCs and microprocessor designs). (a) Significant increase in the number and the diversity of systems that are implemented on a single chip (b) Further exacerbation of old problems and the introduction of new ones such as electrical/physical effects like power dissipation and leakage/temperature issues at all levels, lithography and manufacturing problems leading to appreciable variability, and reliability of the design stemming from reduced feature sizes, to name a few. These issues present significant challenges to the entire range of EDA tools from ESL (e.g., memory synthesis and hierarchy design, effective power analysis and optimization) gate-level synthesis (e.g., detailed power optimization across millions of gates under timing yield and voltage-island constraints). EDA software has thus become immensely complex, and algorithmic innovations are needed to tackle these new problems with efficiency and efficacy at various stages of the VLSI design flow (e.g., ESL including high-level synthesis, logic/physical synthesis, physical extraction and timing models, variability/manufacturing aware optimization, simulation and analysis, and verification).

We are thus asking for original paper submissions addressing critical problems in EDA using effective algorithmic techniques that are either new or uncommon in EDA. More formally put, the desired algorithmic techniques are those that either (a) are completely new in their usage in the EDA domain, or (b) have been proposed only over the last five years or so or (c) have been proposed more than five years back, but have been used sparsely in EDA. Potential topics include, but are not limited to:

  • Various polynomial time approximation schemes (e.g., PTAS, EPTAS, FPTAS)
  • Randomized algorithms
  • Discretized network flow (DNF)
  • Multilevel techniques for scalability
  • Parallel processing (especially for multicore CPU/GPU processors) including concurrent data structures
  • Metaheuristics, for example, tabu search, greedy randomized adaptive search procedures (grasp), ant colony optimization, multistart methods, and constraint satisfaction
  • Machine learning and statistical techniques
  • Data mining techniques

The proposed algorithms should empirically demonstrate efficacy in solving the targeted EDA problems. When submitting your paper to this special issue, please include a new section titled “New Algorithmic Technique(s) Used” that immediately follows the “Introduction” section, for an explicit identification of the algorithmic technique(s) used, and a justification, possibly with citations, that they fit into one of the above categories (a–c). Also, as with any other journal publication, if the submission is an extension to a conference paper, please also include a paragraph of justification in the “Introduction” section (at least 30% new material is required).

Before submission authors should carefully read over the journal's Author Guidelines, which are located at Prospective authors should submit an electronic copy of their complete manuscript through the journal Manuscript Tracking System at according to the following timetable:

Manuscript DueFriday, 30 March 2012
First Round of ReviewsFriday, 29 June 2012
Publication DateFriday, 24 August 2012

Lead Guest Editor

  • Shantanu Dutt, Department of Electrical and Computer Engineering University of Illinois at Chicago, Chicago, IL, USA

Guest Editors

  • Dinesh Mehta, Department of Electrical Engineering and Computer Science, Colorado School of Mines, Golden, Co, USA
  • Gi-Joon Nam, IBM Research Labs, Austin, TX, USA