VLSI Design

VLSI Circuits, Systems, and Architectures for Advanced Image and Video Compression Standards


Publishing date
18 May 2012
Status
Published
Submission deadline
18 Nov 2011

1VLSI Laboratorio, Dipartimento di Elettronica, Politecnico di Torino, Torino, Italy

2Chair for Embedded Systems (CES), Department of Computer Science, Karlsruhe Institute of Technology (KIT), Karlsruhe, Germany

3Ericsson Research, Stockholm, Sweden


VLSI Circuits, Systems, and Architectures for Advanced Image and Video Compression Standards

Description

Modern image and video standards achieve very high compression ratios and include several coding modes in order to address applications with different requirements ranging from low-complexity to high-quality/high-end applications. Significant examples of such applications are portable devices (such as 2D/3D camcorders, cameras, cell phones, PDAs, and tablets) and home-theatre products (like DVD/blue-ray players, digital decoders, DTVs, and 3DTVs). In this scenario, JPEG-XR, 3D/multiview video coding, and upcoming H.265/HEVC (high efficiency video coding) are the cutting-edge standards that have gained significant academic, research, and industrial interest. However, these standards exhibit high complexity and memory/bandwidth requirements primarily due to complex and context-aware processing, adaptive/scalable algorithms, high-resolution frames, and high throughput/frame rate constraints. Moreover, several applications, including portable and wireless image/video communications, pose severe constraints on the power consumption. The power issue (especially leakage) becomes an imperative design criterion in the era of submicron/nano fabrication technology nodes.

As a consequence, VLSI circuits, systems, and architectures are mandatory to effectively address the above-mentioned challenges and application demands/characteristics with low power consumption. Furthermore, interoperability among different standards is an added value that can be achieved by the means of multifunctional, flexible, and adaptive circuits, systems, and architectures.

This special issue is dedicated to research problems and innovative solutions in all aspects of design and architecture addressing realization issues of cutting-edge standards for image and video compression. Authors are encouraged to submit high-quality research contributions. Submissions with focus on industrial value/potential are appreciated.

The following topics qualify for the special issue, where for each topic, work on advanced image and video compression standards with a consideration of important system metrics (like high performance, high throughput, low power, complexity, area, flexibility, and adaptivity) is encouraged. Potential topics include, but are not limited to:

  • Architectures, microarchitecture, circuits, and systems
  • VLSI implementations
  • Multifunctional architectures and support for multistandards
  • Adaptive and reconfigurable solutions
  • Power-/energy-aware computing
  • Memory (sub)systems and memory management
  • Architecture exploration and optimization for computation, communication, and memory
  • Multicore and multiprocessor solutions
  • SoC/multicore architecture and hardware implementation targeting advanced video coding

Before submission authors should carefully read over the journal's Author Guidelines, which are located at http://www.hindawi.com/journals/vlsi/guidelines/. Prospective authors should submit an electronic copy of their complete manuscript through the journal Manuscript Tracking System at http://mts.hindawi.com/ according to the following timetable:


Articles

  • Special Issue
  • - Volume 2012
  • - Article ID 102585
  • - Editorial

VLSI Circuits, Systems, and Architectures for Advanced Image and Video Compression Standards

Maurizio Martina | Muhammad Shafique | Andrey Norkin
  • Special Issue
  • - Volume 2012
  • - Article ID 298396
  • - Research Article

Automatic Generation of Optimized and Synthesizable Hardware Implementation from High-Level Dataflow Programs

Khaled Jerbi | Mickaël Raulet | ... | Mohamed Abid
  • Special Issue
  • - Volume 2012
  • - Article ID 752024
  • - Research Article

𝑁 Point DCT VLSI Architecture for Emerging HEVC Standard

Ashfaq Ahmed | Muhammad Usman Shahid | Ata ur Rehman
  • Special Issue
  • - Volume 2012
  • - Article ID 602737
  • - Research Article

Hardware Design Considerations for Edge-Accelerated Stereo Correspondence Algorithms

Christos Ttofis | Theocharis Theocharides
  • Special Issue
  • - Volume 2012
  • - Article ID 209208
  • - Research Article

Optimized Architecture Using a Novel Subexpression Elimination on Loeffler Algorithm for DCT-Based Image Compression

Maher Jridi | Ayman Alfalou | Pramod Kumar Meher
  • Special Issue
  • - Volume 2012
  • - Article ID 413747
  • - Research Article

An Efficient Multi-Core SIMD Implementation for H.264/AVC Encoder

M. Bariani | P. Lambruschini | M. Raggio
  • Special Issue
  • - Volume 2012
  • - Article ID 748019
  • - Research Article

Low-Complexity Hierarchical Mode Decision Algorithms Targeting VLSI Architecture Design for the H.264/AVC Video Encoder

Guilherme CorrĂȘa | Daniel Palomino | ... | Luciano Agostini
  • Special Issue
  • - Volume 2012
  • - Article ID 242989
  • - Research Article

Low Cost Design of a Hybrid Architecture of Integer Inverse DCT for H.264, VC-1, AVS, and HEVC

Muhammad Martuza | Khan A. Wahid

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