VLSI Design

High Performance Bus-Based Architectures


Status
Published

Guest Editors
Stephan Olariu | Rong Lin

High Performance Bus-Based Architectures

Articles

  • Special Issue
  • - Volume 9
  • - Article ID 037271

Finding Combined L1 and Link Metric Shortest Paths in the Presence of Orthogonal Obstacles: A Heuristic Approach

Joon Shik Lim | S. Sitharama Iyengar | Si-Qing Zheng
  • Special Issue
  • - Volume 9
  • - Article ID 068076

Guest Editorial

Stephan Olariu | Rong Lin
  • Special Issue
  • - Volume 9
  • - Article ID 071739

Single Step Undirected Reconfigurable Networks

Yosi Ben-Asher | Assaf Schuster
  • Special Issue
  • - Volume 9
  • - Article ID 075313

Partitionable Bus-based String-matching Algorithm for Run-length Coded Strings With VLDCs

Hsiu-Niang Chen | Kuo-Liang Chung
  • Special Issue
  • - Volume 9
  • - Article ID 032697

Multiplication of Matrices With Different Sparseness Properties on Dynamically Reconfigurable Meshes

Martin Middendorf | Hartmut Schmeck | ... | Gavin Turner
  • Special Issue
  • - Volume 9
  • - Article ID 025362

Sorting on Reconfigurable Meshes: An Irregular Decomposition Approach

Ten H. Lai | Ming-Jye Sheng
  • Special Issue
  • - Volume 9
  • - Article ID 029035

Investigation of Various Mesh Architectures With Broadcast Buses for High-Performance Computing

Sotirios G. Ziavras
  • Special Issue
  • - Volume 9
  • - Article ID 079875

Reconfigurable Shift Switching Parallel Comparators

R. Lin | S. Olariu