In this paper, we describe a highly efficient automatic test pattern generator for stuck-open (SOP) faults, calledSOPRANO, in CMOS combinational circuits. The key idea of SOPRANO is to convert a CMOS circuit into anequivalent gate level circuit and SOP faults into the equivalent stuck-at faults. Then SOPRANO derives testpatterns for SOP faults using a gate level test pattern generator. Several techniques to reduce the test set sizeare introduced in SOPRANO. Experimental results performed on eight benchmark circuits show that SOPRANOachieves high SOP fault coverage and short processing time.

Hyung K. Lee

Dong S. Ha

An Efficient Automatic Test Pattern Generator forStuck-Open Faults in CMOS Combinational Circuits

The testability distribution of a VLSI circuit is modeled as a series of step functions over the interval [0, 1]. Themodel generalizes previous related work on testability. Unlike previous work, however, we include estimates oftestability by random vectors. Quadratic programming methods are used to estimate the parameters of thetestability distribution from fault coverage data (random and deterministic) on a sample of faults. The estimatedtestability is then used to predict the random and deterministic fault coverage distributions without the need toemploy test generation or fault simulations. The prediction of fault coverage distribution can answer importantquestions about the &#8220;goodness&#8221; of a design from a testing point of view. Experimental results are given on thelarge ISCAS-85 and ISCAS-89 circuits.

H.  Farhat

S.  From

A Quadratic Programming Approach to Estimatingthe Testability and Random or DeterministicCoverage of a VLSl Circuit

In this paper, we describe algorithms based on Simulated Annealing for selecting a subset of flip-flops to be
connected into a scan path. The objective for selection is to maximize the coverage of faults that are aborted by
a sequential fault simulator. We pose the problem as a combinatorial optimization, and present a heuristic algorithm
based on Simulated Annealing. The SCOAP testability measure is employed to assess the selection of flip-flops
during the course of optimization. Our algorithms form a part of an integrated design package, TOPS, which has
been designed as an enhancement to the OASIS standard-cell design automation system available from MCNC.
We discuss the TOPS package and its performance on a number of ISCAS'89 benchmarks. We also present a
comparative evaluation of the benchmark results.

C. P. Ravikumar

H. Rasheed

TOPS: A Target-Oriented Partial Scan Design
Package Based on Simulated Annealing

The use of associative memories&#8212;storage devices that allow data retrieval based on contents&#8212;has often beensuggested to speed up the performance of many applications. Until recently, using such content-addressablememories (CAMs) was unfeasible due to their high hardware cost. However, the advent of VLSI has made theclass of fully-parallel associative memory cost-effective for implementation. This paper briefly overviews designof several fully parallel associative memories proposed in the literature, concentrating on the design of fully-parallel&#952;-search CAMs.Existing market realities require that product development be fast and predictable. As a result, design flexibilityand automation are becoming increasingly important design features. Using the various CAM designs reviewed,the paper collects the features of these designs into a general, modular CAM organization and describes its majorcomponents. The modular CAM organization can be used to design application specific CAMs of varying degreesof functionality. Design and space complexity of a sample associative memory suitable for relational databaseoperations is studied. Finally, the application of genetic algorithms as a means to developing automated designtools for fabrication of modular VLSI design chips is discussed.Given a library of CAM modules, the desired functionality and a set of speed and area constraints, thisoptimization technique produces a suitable CAM design. The proposed technique has been implemented and itsperformance measure is briefly addressed.

A. R. Hurson

S.  Pakzad

Modular Scheme for Designing Special PurposeAssociative Memories and Beyond

In this paper, we present a Simulated Evolution Gate Matrix layout Algorithm (SEGMA) for synthesizing CMOS
random logic modules. The gate-matrix layout problem is solved as a one-dimensional transistor gates placement
problem. Given a placement of all the transistor gates, simulated evolution offers a systematic method to improve
the quality of the layout that is measured by the number of tracks needed for the given netlist. This is accomplished
by identifying a subset of gates whose relative placements are deemed “poor quality” according to a heuristic
criterion. By rearranging the placement of these identified subsets of gates, it is hoped that a gate placement with
better quality, meaning fewer tracks, may emerge. Since this method enables the current “generation” of gate
placement to evolve into a more advanced one in a way similar to the biological evolution process, this method
is called simulated evolution. To apply simulated evolution to solve the gate-matrix layout problem, we propose
a novel heuristic criterion, called randomized quality factor, which facilitates the judicious selection of the subset
of poor quality gates. Several carefully devised and tested strategies are also implemented. Extensive simulation
results indicate that SEGMA is producing very compact gate-matrix layouts.

Chi-Yu Mao

Yu   Hen Hu

SEGMA: A Simulated Evolution Gate-Matrix Layout
Algorithm

This paper presents techniques for designing arbitrary combinational circuits so that any single stuck-at fault will
result in either single bit error or unidirectional multibit error at the output. If the outputs are encoded using
Berger code or m-out-of-n code, then the proposed technique will enable on-line detection of faults in the circuit.
An algorithm for indicating whether a certain fault at an input will create bidirectional error at the output is
presented. An input encoding algorithm and an output encoding algorithm that ensure that every fault will either
produce single bit error or unidirectional multibit error at the output are proposed. If there are no input fault
which produces bidirectional error, no internal stuck-at fault will result in such an error irrespective of the way
the circuit is implemented. Thus, only single bit or unidirectional multibit error will result in the presence of a
fault in the circuit. The proposed techniques have been applied to MCNC benchmark circuits and the overhead
is estimated.

Fadi Busaba

Parag K. Lala

Techniques for Self-Checking Combinational Logic
Synthesis

An efficient, unified algorithm, Advanced Two-Phase Cluster Partitioning, is proposed for automated synthesis
of pseudo-exhaustive test generator for Built-In Self-Test (BIST) design. A prototype of the algorithm, Two-Phase Cluster Partitioning, has been proposed and the hierarchical design procedure is computationally efficient
and produces test generation circuitry with low hardware overhead. However, in certain worst case, the algorithm
may generate a sub-optimal design which requires more test patterns and/or hardware overhead. In order to
generate a globally optimal design, further improvement of two-phase algorithm can be achieved by expanding
the design space for the formation of linear sum so that the number of test signals required for pseudo-exhaustive
testing can be reduced. We demonstrate the effectiveness of our approach by presenting detailed comparisons of
our results against those that would be obtained by existing techniques.

Chien-In Henry Chen

Partitioning Techniques for Built-In Self-Test Design

The high degree of parallelism in the simulation of digital VLSI systems can be utilized by a data flow architecture
to reduce the enormous simulation times. The existing logic simulation accelerators based on the data flow principle
use a static data flow architecture along with a timing wheel mechanism to implement the event driven simulation
algorithm. The drawback in this approach is that the timing wheel becomes a bottleneck to high simulation
throughput. Other shortcomings of the existing architecture are the high communication overhead in the arbitration
and distribution networks, and reduced pipelining due to a static data flow architecture. To overcome these, three
major improvements are made to the design of a classical data flow based logic simulation accelerator. These
include:1) A novel and efficient technique for implementing a pseudo-dynamic data flow architecture to increase
pipelining.2) Implementation of a modified distributed event driven simulation algorithm.3) Localized processors for fast evaluation of small primitives.

A. Mahmood

J. Herath

J. Jayasumana

An Improved Data Flow Architecture for Logic
Simulation Acceleration

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Articles

An Efficient Automatic Test Pattern Generator for Stuck-Open Faults in CMOS Combinational Circuits

A Quadratic Programming Approach to Estimating the Testability and Random or Deterministic Coverage of a VLSl Circuit

TOPS: A Target-Oriented Partial Scan Design Package Based on Simulated Annealing

Modular Scheme for Designing Special Purpose Associative Memories and Beyond

SEGMA: A Simulated Evolution Gate-Matrix Layout Algorithm

Techniques for Self-Checking Combinational Logic Synthesis

Partitioning Techniques for Built-In Self-Test Design

An Improved Data Flow Architecture for Logic Simulation Acceleration