Abstract
Wireless chip area network which enables wireless communication among chips fosters development in wireless communication and it is envisioned that future hardware system and developmental functionality will require multimaterial. However, the traditional system architecture is limited by channel bandwidth-limited interfaces, throughput, delay, and power consumption and as a result limits the efficiency and system performance. Wireless interconnect has been proposed to overcome scalability and performance limitations of multihop wired architectures. Characterization and modeling of channel become more important for specification of choice of modulation or demodulation techniques, channel bandwidths, and other mitigation techniques for channel distortion and interference such as equalization. This paper presents an analytical channel model for characterization, modeling, and analysis of wireless chip-to-chip or interchip interconnects in wireless chip area network with a particular focus on large-scale analysis. The proposed model accounts for both static and dynamic channel losses/attenuation in high-speed systems. Simulation and evaluation of the model with experimental data conducted in a computer desktop casing depict that proposed model matched measurement data very closely. The transmission of EM waves via a medium introduces molecular absorption due to various molecules within the material substance. This model is a representative of channel loss profile in wireless chip-area-network communication and good for future electronic circuits and high-speed systems design.
1. Introduction
Interchip wireless communication has attracted research attention in recent time as present-day exclusively wired communication and circuit dimensions get smaller. Specifically, the rapid emergence of integrated circuits (ICs) and systems on flexible and organic substrates for wearable and implantable electronics, Internet of Things (IoT) or Internet of Everything (IoE), data center, multicore computers, multilayer sensor networks, and so on require effective coupling for adequate and optimum performance of the systems [1, 2]. Since there is high system multifunctionality demand, it is envisioned that multimaterial high-speed system will surface in the nearest future. Wireless IC design has power reduction, latency reduction, and aggregate higher data rates than processing cores which intercommunicates with the ultimate goal to alternate wired interconnect. Furthermore, logically deployed high-speed ultrashort range wireless links integrated platforms will provide improvements in efficiency, weighty reduction in size and complexity; fault tolerance; reconfigurability; and overall performance [3]. A major characteristic quality of the twenty-first century integrated electronics has been the emergence of wireless interconnect and explosive development of multifunctional and handy devices with sub-10 GHz communications as future requires higher bandwidths and data rates with ultra-low power systems connected in very short length scales [2]. Another integrity of wireless interconnect systems includes low complexity compared to wired connections; high energy efficiency for long, one-hop communication; and compatibility with CMOS wireless technology designs. Interconnects in multicore high performance computing architectures are the major drivers of such inconsistent requirements for design with mobile data cloud and intraroom multimedia [2, 4–9]; channel path loss quantification/model becomes necessary for specification of choice of channel bandwidths and any mitigation technique for channel distortion and interference such as equalization (e.g., filter) for adequate systems design.
Attempts have been made by different researchers such as [1, 10–16] to model the propagation pattern in on-chips but less attention on interchip communication [13, 17] and the general free space path loss model [18] remains unattended. Since interchip communication is key in system designs, then it becomes necessary to have an estimated path loss for adequate systems design. Recently, [2] designed an ultralow power wireless interconnects for network-on-chip and chip-to-chip communications by optimization of inductor-less two-stage cascode cascade LNA towards 90 GHz operation. It gains switching advantage against CMOS counterpart without additional switching transistors which consequently makes it highly power efficient and faster. Chen and Zhang [17] modeled path loss for interchip wireless communication channel from measurements. However, environment of propagation was assumed uniform (i.e., single material) which may not be valid for future multimaterial system hardware and development applications; for example, applying the model for circuits on PCB (printed circuit board) made of silicon and polyimide materials may be challenging, and frequency dependency is another key factor that should be considered because loss intensity changes with frequencies.
Adequate path loss characterization and modeling of interconnect in high-speed systems remain an open challenge and as a result requires more research attentions. Robust channel models are still required for the proper and appropriate characterization of interchip channels. In this paper, an analytical channel model which was validated by practical experimental data obtained from a computer desktop casing is proposed. The proposed model is frequency dependent and environmental material property dependent (dielectric property) which make it more robust and better for interchip large-scale path loss prediction. Introduction is presented in Section 1. Section 2 shows the proposed model while measurements and analysis are presented in Section 3. Section 4 presents model simulation and evaluation and Section 5 concludes the paper.
2. Proposed Analytical Model
A wireless channel can be characterized as an open-loop system with both static and dynamic changes of the channel parameterized. Figure 1 is a representation of a typical open-loop system; is the input signal, is the channel response, is the noise, and is the output signal which is given as [19]Signal propagating wirelessly is inversely proportional to a certain degree (say ) of its distance . The ratio of output signal to input signal varies directly to wavelength while its constant of proportionality defines the links parameters (electrical properties of the channel) such as effective permeability , and it is the effective dielectric constant, effective permittivity which implies the dielectric constant of a homogeneous medium that replaces air, depending on the nature of the material, signal source core/chip gain , and receiving core/chip gain . The combined noise effect of all the above parameters can act as noise source that is mentioned in (1). Therefore, the constant of proportionality can be expressed asfor a uniform material propagation path (e.g., silicon), effective permittivity and permeability will be a constant value each. However for multilayer dielectric structures which are found in the present semiconductor industry, effective modeling of these structures enhances fast and accurate analysis and reduced computational cost. Teng [20] presents an extended Maxwell-garnet model ((3) and (4) are general expression for permittivity and permeability, resp.) which can be used to model effective permittivity and permeability. The extraction procedure for effective constitutive parameters is well detailed in [20] where subscripts and represent the permeability and permittivity of matrix material and inclusion material, respectively, while p is the volume fraction of the inclusion and is the frequency dependent term defined as where a is the radius of the sphere inclusion.
As signal propagates through the channel wirelessly on PCB, it varies with frequency variation, and hence a factor is introduced. is frequency, and accounts for other losses due to interference, dispersion, and so on of the channel. Therefore (3) by substitution can be expressed asPractically, there is no ideal environment, and then . At any point of signal observation, signal received is given asEquation (11) can therefore be used to predict signal intensity at any point of observation. Conversely, loss and received signal intensity are inversely related to each other (see (8) [2]); by substitution and logarithmic approach, loss givesFor single layer dielectric structure,For multilayer dielectric structures,where is in Hz, the space between cores/chips can be in mm (millimeter), μm (micrometer), cm centimeter, and so on depending on application and technology, is the reference distance, is in Hz, is the reference attenuation in dB, is the zero mean Gaussian distributed random variable (dB), is the speed of light, and and account for interference, dispersion, noise, and so on which are frequency dependent. Exponents and are the power loss factor which could be determined by fittings from measurement data.
3. Measurement and Analysis
An interchip channel measurement using a computer motherboard or computer casing was conducted. It was difficult to put antenna close to mounted chip surface because of large-area chips which are not readily available and presence of discrete components. Hence, two UWB antennas (structure appears in Figure 2) whose measured impedance bandwidths were placed vertically with a right angle connector. The employed UWB antenna has free space measured shown in Figure 3 lower than −10 dB over 6.7 GHz from 3.75 to 10.45 GHz and the measured free space radiation patterns in E and H planes are shown in Figure 4 where the antenna display quasi omnidirectional patterns. Normalized transfer function and group delay are given in Figure 5. For proper channel sounding in the computer motherboard, pair of 20 cm semiflexible cable was positioned between antennas and network analyzer cables. The network analyzer employed is an Agilent PNA-L network analyzer of model N5230A up to 20 GHz and measurements were carried out on a typical commercial desktop LENOVO computer case, where different components such as hard drive, floppy drive, zip drive, memory, and graphic card are mounted.
(a)
(b)
(c)
(d)
The measurement setup appears in Figure 6 and a photograph is shown in Figure 7. For all measurements taken, the computer case was placed on laboratory electronic work bench and recording was taken for both closed and open of computer case. No object was moving around during measurement and for closed computer case, the closure was well shielded against any outside interferences. Hence, the multipath channel is frozen or quasistatic. CPU fan and heat-sink were removed for the convenient measurement and sampling frequency range chosen is 3.1–10.6 GHz in order to obtain the highest allowable emitting power under FCC regulations. Series of measurements were taken: between CPU and chip Y: transmitting antenna positioned on top of chip Y and receiving antenna moves on the grids of CPU; chip X and CPU: there was non-line-of-sight due to graphic card inside the case, transmitting antenna positioned on chip X and receiving antenna on the grids of central processing unit.
Figure 8 shows typical NLOS received power when computer case is closed curve fittings of path loss to the proposed model which was performed in Matlab with 95% confidence level and parameter extracted is as summarized in Table 1 while fittings of path loss scatter plot are as shown in Figure 9. Discrete components in close proximity of antennas during measurements altered antenna characteristics and the effect cannot be calibrated out from sampled chip-to-chip interconnect response. Path loss factors were affected by multipath in the computer case. In computer closed case, energy bounces inside the case which consequently leads to lower path loss factor and low power attenuation. During open case scenario, energy goes out of the case while the remaining portion got reflected and as a result leads to higher path loss factor and power loss. Path loss between casing closed and casing opened increases when interconnect distance increases. Reflected energy from metal cover is firstly collected before scattering out, the intensity which is a function of metallic material properties (formulated in the reference path of the proposed model). It was observed that the closed casing has more uniform environment because of lower shadowing effect .
(a) -value for close
(b) -value for open
(c) -value for close
(d) -value for open
4. Model Simulation and Evaluation
As shown in Figure 10, proposed model matches the experimental results closely, and this shows that fitted parameters appearing in Table 1 are appropriate and therefore suitable for chip-to-chip interconnecting. It can be used to abstract the actual propagation characteristics of electromagnetic waves utilized for conveying certain information in a compact or open form. Generally, the model developed is appropriate for the characterization and modeling of interconnects in chip-to-chip wireless communication. In the past, various models have been developed to adequately predict channel path loss but none considered dielectric material effect and because characteristic impedance of transmission line varies with the material property, this yields the reflection loss due to mismatched impedance at the source and load of transmission line. Also loss tangential factor of each material has significant effect on the loss profile. Electromagnetic permeability in free space is approximately H/m while permittivity varies with material property. Four dielectric materials were tested; that is, silicon, Teflon, beryllia, and gallium arsenide were examined to show electromagnetic propagation in a nonuniform material at 10 GHz and the results are shown in Figure 11. Dielectric material loss intensity varies from material to material; this must therefore be considered for efficient wireless chip network designs. A quantitative comparison between previous path loss models for chip-to-chip communication and the proposed model becomes important, thereby given in Table 2. Power decay rate change over distance in Figure 12 is explained by where , , and are the slope, T-R distance in mm, and decay rate at zero interception distance, respectively. The decay rate parameters over distance are summarized in Table 3. It can be observed that decay rate is higher with opened case than that of the closed case; this is because closed case allows signal to bounce more time before it decays completely. Negative values imply that when T-R distance increases, signal has more paths to arrive at the receiving antenna consequently resulting in a lower time decay rate. Open case steeper slope indicates that increase in the number of paths in proportion to T-R distance is more important for open case scenario. For closed case, there present many paths even for short distance due to the closed environment; hence, increase in number of paths due to increase in T-R distance is not as critical as that in open case. The variation of energy among grids of chips has been investigated in small scale analysis presented in Chen and Zhang [17] while this work focuses mainly on large-scale analysis. As signal propagates through the medium with multimaterial causes different level of absorption as a result of different molecules presents in the material substances. The proposed model is therefore adequate for interchip interconnects path loss characterization and modeling for effective electronic circuits and systems designs.
5. Conclusion
In this paper, an analytical channel model has been proposed for the interconnect characterization and modeling of wireless chip-to-chip network in single and multimaterial high-speed system design. The transmission of EM waves via a medium causes molecular absorption due to various molecules within the material substance. The statistical analysis of interchip wireless interconnect evaluated with measurement data in a desktop computer cases which represents practical interchip wireless platform and a close matching was observed. It equally incorporates dielectric material property of the environment of propagation which turned out to be an important factor in system design. The proposed model is recommended for interchip wireless interconnect characterization and modeling towards efficient and adequate electronic circuits and systems design.
Conflicts of Interest
The authors declare that there are no conflicts of interest regarding the publication of this paper.
Acknowledgments
Experiment was conducted in Micro-/Nano-Electronic System Integration Center of USTC. This work is financially supported by CAS-TWAS president fellowship.