Abstract
This paper implements a complementary Class-C digitally controlled oscillator (DCO) with differential transistor pairs. The transistors are dynamically biased by feedback loops separately benefiting the robust oscillation start-up with low power consumption. By optimizing three switched capacitor arrays and employing fractional capacitor array with sigma-delta modulator (SDM), the presented DCO operates from 3.22 GHz to 5.45 GHz with a 51.5% frequency tuning range and 0.1 ppm frequency resolution. The design was implemented in a 65 nm CMOS process with power consumption of 2.8 mA at 1.2 V voltage supply. Measurement results show that the phase noise is about −126 dBc/Hz at 3 MHz offset from a 5.054 GHz carrier frequency with the corner frequency of 260 KHz. The resulting FoMT achieves 199.4 dBc/Hz and varies less than 2 dB across the frequency tuning range.
1. Introduction
Combining the high spectral purity, wide FTR, and low power consumption is still one of the most challenging targets in the design of frequency synthesizers, especially for the cellular GSM/WCDMA/LTE applications. In recent years, ADPLLs are deeply researched and widely used in cellular applications because of their downscaled area, low power consumption, and improved phase noise performance in advanced CMOS technology [1, 2]. DCO is one of the most challenging design blocks because good phase noise performance should be ensured with low power consumption and it needs to satisfy the wide FTR and high-frequency resolution simultaneously in ADPLL.
Compared with traditional LC-tank oscillators, the differential transistor pairs based Class-C oscillator delivers briefer and taller pulses and maximizes the output oscillation amplitude, which leads to a minimization of the phase noise [3]. It means that the phase noise can be improved theoretically with the same current consumption.
This paper implements a wide FTR and high FoMT Class-C DCO based on 65 nm 1P9M CMOS process. Two feedback loops ensure the robust oscillation start-up of DCO [4, 5], which is achieved by adjusting the DC biasing voltage of the differential transistor pairs synchronously reducing power consumption. The FTR and frequency resolution of the presented DCO are improved and optimized by employing the three capacitor arrays and the fractional array with SDM.
The remaining paper is divided into three parts. Description of the presented complementary Class-C DCO is given in Section 2 and measurement results are shown in Section 3. Conclusion is described in Section 4.
2. Complementary Class-C DCO
2.1. Architecture Description
Figure 1 shows the complementary Class-C DCO architecture. Two cross-coupled pairs and provide negative resistance to recover the energy losses in the resonant load. The current mirror is made up of and to provide the dc current bias, and it also has a high enough transconductance initially by using the negative feedback to ensure a robust start-up oscillation. Moreover, in steady state, the bias voltage falls from its start-up value which maximizes the output swing [4]. works as a level shifter to provide dc bias voltages and through the common-mode negative feedback. LC-tank is composed of a tapped inductor and three capacitor arrays.
2.2. Design of Capacitor Arrays
DCO’s resonant frequency can be tuned by switching the varactors between on-state and off-state as (1), in which , , andare the varactor’s off-state capacitance value, digitally controlled signal, and , separately. is the capacitance differential value between the on-state and off-state and is the whole parasitic capacitance. Capacitor arrays include coarse array, medium array, and fine array and their corresponding FTS are , , and , respectively. The capacitor arrays are constructed by PMOS varactor because of its high density capacitance.
For coarse array, is proportional to the inductor value , , and the cube of as shown in (2):
Equation (3) gives the -domain open loop transfer function of ADPLL [2], and are loop parameters, is reference clock, and is the normalized gain of DCO. In coarse array, changes 4.85 times (≈(5.45/3.22)3) across the entire FTR, and ADPLL’s also changes with as (3), which will result in instability of ADPLL loop. Therefore, varactors with different value are adopted at different frequency points realizing a constant to ensure the loop stability.
For LC-DCO, the and the can be calculated by (4), where , , and are the , the , and all the capacitors of the coarse array, respectively. In order to get constant , should be equal to , which means
From (5), it can be concluded that the linearity of only depends on . Finally, the coarse array is designed according to (2)~(5) with constant 24 MHz/LSB’s which is equal to the reference clock 24 MHz. 89 varactors make up the coarse array to cover the wide FTR and they are decoded from 7 bits coarse oscillator tuning word (OTW), as shown in Figure 1; the postfixes _C, _M, _FI, and _FF are, respectively, the OTW of coarse array, medium array, integral fine array, and fractional fine array.
For the wide FTR application, the coarse array has the varactors with the biggest in the resonant tank. For PMOS varactor shown in Figure 2, the relevant parasitic capacitance can be classified into three parts as shown in Figure 2: the oxide layer capacitance between gate and channel: , where is the capacitance of gate oxide layer per unit area and and are the gate width and gate length, respectively; the depletion layer capacitance between substrate and channel: , where is a charge constant, is the dielectric constant of silicon, is the doping concentration of N-well, andis the built-in potential; the overlapping capacitance among gate, source, and drain: and equal to , where is the overlapping capacitance per unit width.
Therefore, when the PMOS varactor operates in inversion region, capacitance is maximized to . When the PMOS varactor operates in depletion region, capacitance is minimized to .
So the capacitance ratio is
Because , increases when is increased, and higher means the wider FTR.
When PMOS varactor operates in depletion region, channel is not formed; the parasitic resistance only includes gate resistance and metal contact parasitic resistance of source and drain , so the value of PMOS varactor in depletion region is
However, when the PMOS varactor lies in inversion region, the value can be inferred from [9] as the following equation shows:
In (8), is the gain factor of PMOS transistor, is the voltage difference between gate and source, and is the threshold voltage for PMOS transistor. It can be concluded that is inversely proportional to the square of .
Therefore, the value, symmetry, and are mainly determined by the coarse array. For the coarse array, it is difficult to trade off the value and the region of FTR. Finally, the channel length of the coarse array is set to 600 nm. As shown in the postsimulation in a 65 nm CMOS process, the value is higher than 25 and the is about 7. Both of them satisfy the phase noise and the FTR requirements.
However, for the medium and fine array, frequency resolution is the most important design factor. 200 nm and 60 nm channel length are chosen, respectively, for high-frequency resolution and high value. Both of them are composed of unit cap array because their FTS varies a little with the change of frequency and these two arrays’ FTS have little effect on the loop stability of ADPLL. The FTR of medium and fine arrays should respectively cover several LSBs of coarse and medium arrays so that the OTW of current array will not overflow due to the process, voltage, and temperature (PVT) variations. In the process of ADPLL locking, OTW overflow means that medium tuning or fine-tuning period cannot be finished and loss-of-lock may occur. According to the possible largest frequency error due to PVT variations and the required frequency resolution of the current locking period, 6-bit medium arrays and 7-bit fine arrays are designed to cover 4 LSBs of and 8 LSBs of , respectively. Finally, the locking process of ADPLL can be divided into three frequency locking periods step by step without the possibility of loss-of-lock due to OTW overflow.
In order to improve the phase noise performance of the DCO, MOS varactor is controlled digitally. As shown in Figure 3, OTW (Oscillator Tuning Word) is decoded into the thermal code to control the on/off states of MOS varactor with an inverting driver. The voltage level of digital control signal can be adjusted by and . Figure 3 also shows the curve of a PMOS varactor capacitance versus (C-V curve). MOS varactors change linearly from to and is the output amplitude of DCO. During the whole oscillation period, the original C-V curve has to be transferred into the average C-V curve with red dashed dotted line as shown in Figure 3. Therefore, in order to stop the PMOS varactor from inducing the noise on the , the varactor must be working in the on/off states region of the average C-V curve.
The finite frequency tuning resolution introduces the quantization noise and contributes the output phase noise of the ADPLL and hence a small tuning step is desired. The frequency resolution requirement is 0.1 ppm, but the smallest FTS is limited by the smallest in 65 nm process. Figure 4 compares the phase noise contribution among MASH 1, MASH 1-1, and MASH 1-1-1 SDM; it can be seen that MASH 1-1-1 SDM has the lowest in-band phase noise contribution and the best noise shaping character. Moreover, their out-band phase noise contributions are almost the same. Therefore, 10-bit OTW_FF is dithered with MASH 1-1-1 SDM to control 6-bit fractional capacitor arrays to improve the frequency resolution and decrease the noise contribution. The phase noise contribution of SDM to ADPLL is simulated with MATLAB as shown and it is below −150 dBc/Hz, which means it affects in a small way the whole phase noise performance. In Figure 5, , , and are the quantization noise of each accumulator. Therefore, the output frequency of SDM can be deduced from
2.3. Class-C DCO’s Negative Feedback Loops
In Figure 1, current is chosen to bias providing a level shift voltage. A RC network is used to provide a dc bias voltage, and is higher than the tank common-mode voltage, which permits a larger resonator swing before the is pushed into the triode region. This is the same technique employed to bias the . Moreover, a high RC constant of the RC biasing network is used to low-pass filter the noise introduced to and , optimizing the phase noise [5]. not only integrates the difference between and the current exhausted by the DCO but also filters the high-frequency noise contribution from , improving the phase noise [4].
The simulated transient voltage of DCO is given in Figure 6(a); is the oscillation output of DCO. Initially, the are diode-connected (at DC) and is mirrored (multiplied by N) to the DCO core, which makes both PMOS and NMOS cross-coupled MOSFET work in saturation region and provide a high transconductance to guarantee a robust start-up. As the oscillator amplitude is increased, the average current depleted by increases and then the superfluous current will be integrated into reducing and guiding the switching pair to work in Class-C mode. At the same time, increases and pushes PMOS working in Class-C mode. is finally changed to the half value of the VDD to offer the common-mode voltage of DCO and the same overdrive of PMOS and NMOS pairs. Figure 6(b) shows the transient simulation result of ’s current (blue line) when operates at Class-C mode; the tall and short pulses maximize the output oscillation amplitude (red line), which minimizes the phase noise of DCO.
(a)
(b)
Referring to the noise analysis in [10], the proposed DCO’s noise from feedback loop can be inferred in (10), where,, and are, respectively, the white noise voltage power spectral density by bias resistor , bias MOSFET , and bias MOSFET . is the single pole in the feedback loop. The is the amplification and frequency translation that the feedback loop noise must undergo first.
Therefore, the total amount of phase noise can be deduced in (11) where is Boltzmann constant, is the absolute temperature in Kelvin, is the capacitor in LC resonant bank, is the oscillation amplitude of DCO, 2R is the parasitics losses, and is the technology coefficient. and are, respectively, weighing factors of cross-coupled MOSFETs and feedback loops.
3. Measurement Results
The Class-C DCO was fabricated in a standard 65 nm CMOS process. Figure 7 offers the die photo of Class-C DCO; it occupies the area of 0.21 mm2 without PADs. Figure 8(a) shows that the different phase noise measurement results in 1 MHz frequency offset at the different resonant frequency, which changes with coarse array code from −118.3 dBc/Hz to −114.8 dBc/Hz. The phase noise measurement results of Class-C DCO with SDM and without SDM at 5.054 GHz are shown in Figure 8(b); the corner frequency is about 260 KHz. Although SDM brings spurs, it can be seen that the phase noise performance with SDM is still better than the phase noise performance without SDM. With SDM, it is −116 dBc/Hz and −126 dBc/Hz at 1 MHz and 3 MHz frequency offset, respectively. Figure 8(c) shows the frequency spectrum of DCO at 3.34 GHz; it can be seen that SDM brings spurs about 10 dBc at point 3 and point 4 on the frequency spectrum of DCO, but it can be suppressed by the loop character of ADPLL. Figure 9 shows that the frequency and change versus the coarse array code. The measured is around 24 MHz/LSB with a maximum deviation of 1.64 MHz/LSB. Figure 10(a) displays the at different frequency points, the red line and the blue line show the at 3.32 GHz and 5.45 GHz, respectively, and changes from 1.5 MHz/LSB to 7.4 MHz/LSB across the whole FTR because is proportional to the cube of as (2) shows. Figure 10(b) gives the at different frequency points, and it changes from 120 KHz/LSB to 455 KHz/LSB through the whole FTR, with the same reason of . After 10-bit SDM, fractional array’s frequency resolution will be divided by 210, so the final frequency resolution varies from 117 Hz to 444 Hz, which is less than 0.1 ppm. When all the varactors change from on-state to off-state, the DCO will work from 3.22 GHz to 5.45 GHz, with the FTR of 51.5%.
(a)
(b)
(c)
(a)
(b)
Table 1 shows the comparison table of state-of-the-art LC-tank oscillators [2, 6–8]. Without the SDM, this DCO has achieved the frequency resolution of 120 KHz, which is close to other references, but it can be 117 Hz after SDM. Reference [8] is also a complementary Class-C DCO, but this work has better performance than it. Reference [6] is traditional LC-DCO; this work shows higher FoM than it due to its Class-C mode. This design works at close frequency with [6–8] while displaying wider FTR and better FoMT due to the design and optimization of capacitor arrays.
4. Conclusion
This paper presented a complementary Class-C digitally controlled oscillator (DCO) with differential transistor pairs. With three optimized capacitor arrays and a fractional array dithered by SDM, the DCO works from 3.22 GHz to 5.45 GHz with 51.5% FTR and less than 0.1 ppm frequency resolution. Through two feedback loops, the start-up oscillation is ensured and low power consumption is realized. The achieved phase noise is −126 dBc/Hz at 3 MHz offset from 5.054 GHz with the corner frequency of 260 KHz while consuming only 2.8 mA at 1.2 V voltage supply. The final FoM and FoMT are 185.2 dBc/Hz and 199.4 dBc/Hz, respectively.
Conflicts of Interest
The authors declare that there are no conflicts of interest regarding the publication of this paper.
Acknowledgments
This work is supported by the National Natural Science Foundation of China (nos. 61574045 and 61774048), the National Science and Technology Major Project (no. 2016ZX03001012-003), and the National High Technology Research and Development Program (no. 2015AA016601-005).