Abstract
This study examines the effects of plasma-induced damage (PID) on Hf-based high-
This study examines the effects of plasma-induced damage (PID) on Hf-based high-
Y. Yoshida and T. Watanabe, “Gate breakdown phenomena during reactive ion etching process,” in Proceedings of the 5th Dry Process Symposium (DPS '83), pp. 4–7, 1983.
View at: Google ScholarS. Krishnan, A. Amerasekera, S. Rangan, and S. Aur, “Antenna device reliability for ULSI processing,” in Proceedings of the International Electron Devices Meeting Technical Digest (IEDM '98), pp. 601–604, San Francisco, Calif, USA, December 1998.
View at: Google ScholarB.-W. Chan, Y. H. Liou, and M.-H. Chi, “Elimination of notch during gate polycide stack etching by adding nitrogen in over etch step,” Proceedings of the 5th International Symposium on Plasma Process-Induced Damage, pp. 54–56, May 2000.
View at: Google ScholarK. M. Byun, D. H. Kim, Y. W. Cha et al., “Reduction of plasma-induced damage during inter metal dielectric deposition in high-density plasma,” in Proceedings of Intergrated Circuit Desing & Technology Conference (ICICDT '05), pp. 99–102, Seoul, Korea, May 2005.
View at: Google ScholarJ. Ackaert, B. D. Eddy, C. Peter, and C. Martin, “Prevention of plasma induced damage on thin gate oxide of HDP oxide deposition, metal etch, ar preclean processing in BEOL sub-half micron CMOS processing,” in Proceedings of the 5th International Symposium on Plasma Process-Induced Damage, pp. 77–80, May 2000.
View at: Google ScholarS. Q. Gu, R. Fujimoto, and M. Peter, “Impact of F species on plasma charge damage in a RF asher,” in Proceedings of the 7th Plasma and Process Induced Damage Symposium, pp. 88–91, Maui, Hawaii, USA, August 2002.
View at: Google ScholarM. L. Green, E. P. Gusev, R. Degraeve, and E. L. Garfunkel, “Ultra thin ( nm) and Si-O-N gate dielectric layers for silicon microelectronics: understanding the processing, structure, and physical and electrical limits,” Journal of Applied Physics, vol. 90, pp. 2057–2121, 2001.
View at: Google ScholarH. Iwai, S. Ohmi, S. Akama et al., “Advanced gate dielectric materials for sub-100 nm CMOS,” in Proceedings of the International Electron Devices Meeting Technical Digest (IEDM '02), pp. 625–628, December 2002.
View at: Google ScholarG. D. Willk, R. M. Wallace, and J. M. Anthony, “High- gate dielectrics: current status and materials properties considerations,” Journal of Applied Physics, vol. 89, pp. 5243–5275, 2001.
View at: Google ScholarS. Zafar, B. H. Lee, J. Stathis, A. Callegari, and T. Ning, “A model for negative bias temperature instability (NBTI) in oxide and high k pFETs,” in Proceedings of the Symposium on VLSI Technology, Digest, pp. 208–209, San Francisco, Calif, USA, 2004.
View at: Google ScholarE. Cartier, B. P. Linder, V. Naryanan, and V. K. Paruchuri, “Fundamental understanding and optimization of PBTI in nFETs with / gate stack,” in Proceedings of the International Electron Devices Meeting Technical Digest (IEDM '06), pp. 321–324, June 2006.
View at: Google ScholarS. C. Song, S. H. Bae, and Z. Zhang, “Impact of plasma induced damage on pMOSFETs with TIN/HF-silicate stack,” in Proceedings of 43th IEEE International Reliability Physics Symposium (IRPS '05), pp. 398–402, San Jose, Calif, USA, April 2005.
View at: Google ScholarC. D. Young, G. Berauker, F. Zhu et al., “Comparison of plasma-induced damage in /TIN and /TIN gate stacks,” in Proceedings of 45th International Reliability Physics Symposium (IRPS '07), pp. 67–70, April 2007.
View at: Publisher Site | Google ScholarM. Koyama, A. Kaneko, T. Ino et al., “Effects of nitrogen in HfSiON gate dielectric on the electrical and thermal characteristics,” in Proceedings of the International Electron Devices Meeting Technical Digest (IEDM '02), pp. 849–852, San Francisco, Calif, USA, December 2002.
View at: Google ScholarM. Koike, T. Ino, and Y. Kamimuta, “Effect of Hf-N bond on properties of thermally stable amorphous HfSiON and applicability of this material to sub -50 nm technology node LSIs,” in Proceedings of the International Electron Devices Meeting Technical Digest (IEDM '03), pp. 107–110, Washington, DC, USA, December 2003.
View at: Google ScholarM. B. Zahid, R. Degraeve, L. Pantisano, J. F. Zhang, and G. Groeseneken, “Defects generation in / studied with variable charge pumping (),” in Proceedings of 45th International Reliability Physics Symposium (IRPS '07), pp. 55–60, April 2007.
View at: Publisher Site | Google ScholarA. T. Krishnan, S. Krishnan, and P. Nicollian, “Impact of gate area on plasma charging damage: the “reverse” antenna effect,” in Proceedings of the International Electron Devices Meeting Technical Digest (IEDM '02), pp. 525–528, December 2002.
View at: Google ScholarK. P. Cheung, C. T. Liu, C. P. Chang et al., “Charging damage in thin-gate-oxides better or worse?” in Proceedings of the 3rd Plasma and Process Induced Damage Symposium, pp. 34–37, Honolulu, Hawaii, USA, June 1998.
View at: Google ScholarK. P. Cheung, “Advanced plasma and advanced gate dielectric—a charging damage prospective,” IEEE Transactions on Device and Materials Reliability, vol. 7, no. 1, pp. 112–118, 2007.
View at: Publisher Site | Google ScholarG. Cellere, M. G. Valentini, and A. Paccagnella, “Correlation between soft breakdown and plasma process induced damage,” in Proceedings of the 6th Plasma and Process Induced Damage Symposium, pp. 40–43, Monterey, Calif, USA, May 2001.
View at: Google ScholarG. Bersuker, J. H. Sim, C. S. Park et al., “Mechanism of electron trapping and characteristics of traps in gate stacks,” IEEE Transactions on Device and Materials Reliability, vol. 7, no. 1, pp. 138–145, 2007.
View at: Publisher Site | Google ScholarG. Van den bosch, B. D. Jaeger, and G. Groeseneken, “Evaluation procedure for fast and realistic assessment of plasma charging damage in thin oxides,” in Proceedings of the 7th Plasma and Process Induced Damage Symposium, pp. 37–40, Maui, Hawaii, USA, August 2002.
View at: Google ScholarR. O'Connor, L. Pantisano, R. Degraeve et al., “SILC defect generation spectroscopy in HfSiON using constant voltage stress and substrate hot electron injection,” in Proceedings of the 46th IEEE International Reliability Physics Symposium (IRPS '08), pp. 324–329, Phoenix, Ariz, USA, April 2008.
View at: Publisher Site | Google ScholarM. Toledano-Luque, L. Pantisano, R. Degraeve et al., “Charge pumping spectroscopy: HfSiON defect study after substrate hot electron injection,” Microelectronic Engineering, vol. 84, no. 9-10, pp. 1943–1946, 2007.
View at: Publisher Site | Google ScholarJ. L. Gavartin, D. M. Ramo, A. L. Shluger, G. Bersuker, and B. H. Lee, “Negative oxygen vacancies in as charge traps in high- stacks,” Applied Physics Letters, vol. 89, no. 8, Article ID 082908, 3 pages, 2006.
View at: Publisher Site | Google ScholarK. Torii, K. Shiraishi, S. Miyazaki et al., “Physical model of BTI, TDDB and SILC in -based high- gate dielectrics,” in Proceedings of the International Electron Devices Meeting Technical Digest (IEDM '04), pp. 129–132, San Francisco, Calif, USA, December 2004.
View at: Google ScholarE. Cartier, F. R. McFeely, V. Narayanan et al., “Role of oxygen vacancies in / stability of pFET metals on ,” in Proceedings of the Symposium on VLSI Technology, pp. 230–231, April 2005.
View at: Publisher Site | Google ScholarK. Shiraishi, K. Yamada, K. Torii et al., “Oxygen vacancy induced substantial threshold voltage shifts in the Hf-based high- MISFET with poly-Si gates—a theoretical approach,” Japanese Journal of Applied Physics, vol. 43, pp. 1413–1415, 2004.
View at: Publisher Site | Google ScholarP. Riess, R. Kies, G. Ghibaudo, G. Pananakakis, and J. Brini, “Reversibility of charge trapping and silc creation in thin oxides after stress/anneal cycling,” Microelectronics Reliability, vol. 38, no. 6-8, pp. 1057–1061, 1998.
View at: Google ScholarJ. W. McPherson and D. A. Baglee, “Acceleration factors for thin oxide breakdown,” Journal of the Electrochemical Society, vol. 132, no. 8, pp. 1903–1908, 1985.
View at: Google ScholarJ. Mcpherson, V. Reddy, K. Banerjee, and H. Le, “Comparison of E and 1/E TDDB models for under logn-term/low field test conditions,” in Proceedings of the International Electron Devices Meeting Technical Digest (IEDM '98), pp. 171–174, San Francisco, Calif, USA, December 1998.
View at: Google ScholarB. J. O'Sullivan, L. Pantisano, P. J. Roussel et al., “On the recovery of simulated plasma process induced damage in high- dielectrics,” in Proceedings of the 44th IEEE International Reliability Physics Symposium (IRPS '06), pp. 365–370, San Jose, Calif, USA, March 2006.
View at: Google ScholarD. Qian and D. J. Dumin, “Field, time and fluence dependencies of trap generation in silicon oxides between 5 and 13.5 nm thick,” Semiconductor Science and Technology, vol. 15, no. 8, pp. 854–861, 2000.
View at: Publisher Site | Google ScholarS. Mahapatra, P. B. Kumar, and M. A. Alam, “Investigation and modeling of interface and bulk trap generation during negative bias temperature instability of p-MOSFETs,” IEEE Transactions on Electron Devices, vol. 51, no. 9, pp. 1371–1379, 2004.
View at: Publisher Site | Google ScholarA. E. Islam, G. Gupta, S. Mahapatra et al., “Gate leakage vs. NBTI in plasma nitrided oxides: characterization, physical principles, and optimization,” in Proceedings of the International Electron Devices Meeting Technical Digest (IEDM '06), pp. 329–333, San Francisco, Calif, USA, December 2006.
View at: Publisher Site | Google ScholarS. Pae, M. Agostinelli, M. Brazier et al., “BTI reliability of 45 nm high-k + metal-gate process technology,” in Proceedings of the 46th IEEE International Reliability Physics Symposium, pp. 352–357, 2008.
View at: Publisher Site | Google ScholarA. T. Krishnan, V. Reddy, and S. Krishnan, “Impact of charging damage on negative bias temperature instability,” in Proceedings of the International Electron Devices Meeting Technical Digest (IEDM '01), pp. 865–868, Washington, DC, USA, December 2001.
View at: Google Scholar