- About this Journal ·
- Abstracting and Indexing ·
- Advance Access ·
- Aims and Scope ·
- Annual Issues ·
- Article Processing Charges ·
- Articles in Press ·
- Author Guidelines ·
- Bibliographic Information ·
- Citations to this Journal ·
- Contact Information ·
- Editorial Board ·
- Editorial Workflow ·
- Free eTOC Alerts ·
- Publication Ethics ·
- Reviewers Acknowledgment ·
- Submit a Manuscript ·
- Subscription Information ·
- Table of Contents
Advances in Materials Science and Engineering
Volume 2013 (2013), Article ID 548329, 5 pages
Charge-Trapping Devices Using Multilayered Dielectrics for Nonvolatile Memory Applications
1Department of Electrical Engineering and Institute of Electronics Engineering, National Tsing-Hua University, Hsinchu 300, Taiwan
2Department of Electronic Engineering, Ming Chuan University, Taoyuan 333, Taiwan
Received 6 August 2013; Revised 31 October 2013; Accepted 2 November 2013
Academic Editor: Tung-Ming Pan
Copyright © 2013 Wen-Chieh Shih et al. This is an open access article distributed under the Creative Commons Attribution License, which permits unrestricted use, distribution, and reproduction in any medium, provided the original work is properly cited.
Charge-trapping devices using multilayered dielectrics were studied for nonvolatile memory applications. The device structure is Al/Y2O3/Ta2O5/SiO2/Si (MYTOS). The MYTOS field effect transistors were fabricated using Ta2O5 as the charge storage layer and Y2O3 as the blocking layer. The electrical characteristics of memory window, program/erase characteristics, and data retention were examined. The memory window is about 1.6 V. Using a pulse voltage of 6 V, a threshold voltage shift of ~1 V can be achieved within 10 ns. The MYTOS transistors can retain a memory window of 0.81 V for 10 years.
One of the most attractive candidates for nonvolatile memory applications is the charge-trapping device in which multilayered dielectrics are used. The semiconductor-oxide-nitride-oxide-semiconductor (SONOS) memory is typical of the charge-trapping devices. The advantages of SONOS-type charge-trapping devices include smaller cell size, lower programming voltage, and better cycling endurance compared with the floating-gate devices. By reducing the tunneling oxide thickness in the SONOS-type devices, faster programming speed and lower operating voltage can be accomplished [1–4]. However, the issues of poor retention time and low erase speed still remain in the SONOS-type memory devices. To improve the retention time of SONOS devices, several researches have been reported. Hsu et al. indicated that HfO2 can replace Si3 N4 and obtain a higher conduction band offset for better retention . Reports showed that the retention of memory devices can be improved using a chemical-vapor-deposited blocking oxide  or implementing a high-temperature deuterium annealing . Additionally, using a high-k dielectric as the blocking oxide, the program/erase speed and retention characteristic can be improved [8, 9]. In the study using Si3 N4, HfO2, and HfAlO as the charge storage layer, Tan et al. showed that larger band offset can improve the program speed and reduce the overerase phenomenon . Furthermore, using the structures of TaN/HfO2/T2 O5/HfO2/Si (MHTHS) and TaN/Al2O3/Ta2O5/HfO2/Si (MATHS) both program speed and retention time can be improved as compared to the traditional SONOS devices [11, 12].
In this work, charge-trapping devices using multilayered dielectrics were studied for nonvolatile memory applications. The structure is metal—yttrium oxide—tantalum oxide—silicon oxide—silicon (MYTOS), that is, Al/Y2O3/Ta2O5/SiO2/Si. The MYTOS devices were fabricated using Ta2O5 as the charge storage layer and Y2O3 as the blocking oxide for both high energy barrier at Al/Y2O3 interface and large dielectric constant. The expected advantages of MYTOS device include longer retention time and faster program/erase speed. Figure 1 shows the energy band diagrams of the MYTOS memory device. The conduction band offset between the tunneling oxide and the high-k charge storage layer is 2.25 eV at the Ta2O5/SiO2 interface. The large conduction band offset is expected to improve the data retention property because the tunneling electrons can be firmly confined into the charge storage layer. In addition, the Ta2O5 trap level is about 2.7 eV  below the conduction band edge which is much deeper than the 1 eV trap level in Si3N4. The deeper trap level is expected to further improve data retention characteristic. Aside from the retention property, the SONOS-type devices with high-k blocking dielectrics can increase the electric field for the tunneling oxide at the same operating voltage used. Hence, the program/erase speed can be improved using a high-k blocking layer. In this work, Y2O3 is chosen to be the blocking oxide in which the charge injection efficiency in the tunneling oxide can be increased; meanwhile, the blocking function can be maintained. The dielectric constant of Y2O3 blocking oxide is about 15 and the conduction band offset at the Ta2O5/Y2O3 interface is about 1.35 eV. This large conduction band offset is expected to give better blocking efficiency which may improve the memory window characteristic. Besides, this high-k blocking layer is expected to increase the program/erase speed as well as to reduce the program/erase voltage.
P-type, (100) orientation, and 4-inch diameter silicon wafers with 1–10 cm resistivity were used as the starting substrates. A 3 nm tunneling oxide (SiO2) was thermally grown by dry oxidation at 900°C. The charge storage layer (Ta2O5) was deposited by RF magnetron sputtering under a pressure of torr at room temperature in argon gas. The purity of Ta2O5 target is 99.9%. The thickness of the Ta2O5 layer is 20 nm. The Ta2O5 films were either as-deposited or annealed at 400°C, 500°C, and 600°C. The annealing was performed in nitrogen at a flow rate of 3 standard cubic centimeters per minute (sccm). After annealing, the blocking layer Y2O3 was deposited by RF magnetron sputtering under a pressure of torr at room temperature in argon gas. The thickness of the Y2O3 blocking layer is 10 nm. For transistor processing, a 500 nm oxide was first grown by wet oxidation and used as the field oxide. The source and drain windows were defined by wet etching and doped by arsenic implantation ( cm−2, 40 keV). The implant was annealed at 950°C in N2 for 30 minutes. The contact region in Ta2O5 was etched by reactive ion etch (RIE) and in SiO2 and Y2O3 by buffered oxide etch (BOE). The 300 nm thick top aluminum electrodes were evaporated by DC sputtering. Postmetallization annealing (PMA) was performed at 400°C in N2 for 30 seconds. The crystalline phase of the high-k dielectric films was identified by X-ray diffraction (Shimadzu XD-5) using Cu Kα radiation. Separate MHHOS capacitors were also fabricated. The characteristics were measured using Keithley 236 electrometer and the characteristics using high-frequency meter MegaBytek Mi-494.
3. Results and Discussion
Figure 2 shows the memory window measurement for MYTOS transistors. The memory window after a 8 V, 0.01 μs program pulse is 1.6 V. The memory window can also be estimated by the capacitance-voltage () hysteresis curves for the MYTOS capacitors. Using a sweep voltage range of 10 V, the memory window of 1.6 V can be achieved due to the electron trapping (not shown here).
Figure 3 shows the programming characteristics of the MYTOS transistors. Pulse voltages of 6 V or 8 V are first applied to the gate. Thus, the electrons can tunnel from Si-substrate into Ta2O5 and be stored into the Ta2O5 charge storage layer which forms a potential well between Si-substrate and Y2O3, as shown in Figure 1. In the program event, Y2O3 is the blocking layer which can prevent the tunneling electrons from passing across the Y2O3 layer since the Y2O3/Ta2O5 interface barrier is high enough. Accordingly, the tunneling electrons can be reserved into the Ta2O5 charge storage layer. The pulse widths are from s to s. After applying the gate pulse, the threshold voltage of the transistor was monitored by measuring the characteristics. is defined as the gate voltage at 1 μA drain current with 0.1 V. The transistor is defined as “programmed” when the shift is larger than 0.5 V. For MYTOS transistors, the shift of more than 0.5 V will occur at an applied voltage of 6 V and with a pulse width 10 ns. For MHTHS  and MATHS , the shift of more than 0.5 V will occur at an applied voltage of 10 V and with pulse widths of 1 ms and 100 ns, respectively. Therefore, low program voltage and fast programming speed were achieved with the MYTOS transistors in this work. The MYTOS transistors thus have faster programming speed and lower program voltage than MHTHS and MATHS memory devices. This is most likely due to the larger conduction band offset of 2.25 eV at the Ta2O5/SiO2 interface compared with 1.2 eV at the Ta2O5/HfO2 interface. At the same gate bias where Fowler-Nordheim tunneling is dominating, the electron tunneling distance from Si-substrate to the conduction band of the storage dielectric is therefore shorter for structures with Ta2O5/SiO2. The large conduction band offset is expected to give better blocking efficiency which will improve memory window and programming speed. In addition, large conduction band offset can also relieve overerase problem. The program voltage of MYTOS transistor can be as low as 6 V, which is lower than that of 10 V for MHTHS  and MATHS . The programming time of 10 ns is also faster than that of 1 ms and 100 ns of MHTHS and MATHS, respectively. As for the erase event, the negative pulse voltage is applied to the Al gate. Hence, the holes can tunnel from Si-substrate into Ta2O5 and recombine the electrons stored into the Ta2O5 layer. Figure 4 shows the erase characteristics of the MYTOS transistors. The transistor is defined as “erased” when the reduces more than 0.5 V. Obviously, an applied gate voltage of −6 V is not enough to do the erase process. Meanwhile, the reduced more than 0.5 V at an applied voltage of −8 V with a pulse width of 0.1 s.
Figure 5 shows the retention characteristic of the MYTOS transistors. The versus characteristic was first measured with a sweep voltage from −3 V to 3 V to determine the original threshold voltage. Pulse voltages of 8 V at 1 ms duration were then applied for program and erase operations. The threshold voltage shift is measured at different time periods. The MYTOS transistors are projected to have a window of 0.81 V after 10 years. Table 1 lists the comprised memory parameters of the charge-trapping devices in which the adopted trapping layers include Ta2O5, Y2O3, HfO2, ZrO2, La2O3, and Dy2O3 [11–20]. The MYTOS shows faster programming time of 10 ns at a low voltage of 6 V.
In summary, Al/Y2O3/Ta2O5/SiO2/Si field effect transistors were fabricated and investigated. The electrical properties, including memory window, program/erase characteristics, and data retention time, were measured. The memory window after 8 V, 0.01 s programming pulse is 1.6 V. The shift of the MYTOS transistors at an applied gate voltage of 6 V with a pulse width of 10 ns is about 1.0 V. As for retention properties, the MYTOS transistors are projected to have a window of 0.81 V after 10 years. The excellent performance of the MYTOS transistors is most likely due to the larger conduction band offset at the Ta2O5/SiO2 and the Y2O3/Ta2O5 interfaces and the large dielectric constant of Y2O3.
Conflict of Interests
The authors declare that there is no conflict of interests regarding the publication of this paper.
The authors would like to thank the National Science Council of the Republic of China, Taiwan, for supporting this work under Contract no. NSC 102-2221-E-130-015-MY2.
- M. H. White, Y. Yang, A. Purwar, and M. L. French, “A low voltage SONOS nonvolatile semiconductor memory technology,” IEEE Transactions on Components Packaging and Manufacturing Technology Part A, vol. 20, no. 2, pp. 190–195, 1997.
- M. French, H. Sathianathan, and M. White, “A SONOS nonvolatile memory cell for semiconductor disk application,” IEEE Nonvolatile Memory Technology Review, pp. 70–73, 1993.
- M. H. White, D. A. Adams, and J. Bu, “On the go with SONOS,” IEEE Circuits and Devices Magazine, vol. 16, no. 4, pp. 22–31, 2000.
- S. Mori, Y. Y. Araki, M. Sato et al., “Thickness scaling limitation factors of ONO interpoly dielectric for nonvolatile memory devices,” IEEE Transactions on Electron Devices, vol. 43, no. 1, pp. 47–53, 1996.
- H.-H. Hsu, I. Y.-K. Chang, and J. Y.-M. Lee, “Metal-oxide-high-κ dielectric-oxide-semiconductor (MOHOS) capacitors and field-effect transistors for memory applications,” IEEE Electron Device Letters, vol. 28, no. 11, pp. 964–966, 2007.
- S.-I. Minami and Y. Kamigaki, “Novel MONOS nonvolatile memory device ensuring 10-year data retention after 107 erase/write cycles,” IEEE Transactions on Electron Devices, vol. 40, no. 11, pp. 2011–2017, 1993.
- J. Bu and M. H. White, “Retention reliability enhanced SONOS NVSM with scaled programming voltage,” in IEEE Aerospace Conference Proceedings, vol. 5, pp. 2383–2390, 2002.
- S. Choi, M. Cho, H. Hwang, and J. W. Kim, “Improved metal-oxide-nitride-oxide-silicon-type flash device with high-k dielectrics for blocking layer,” Journal of Applied Physics, vol. 94, no. 8, pp. 5408–5410, 2003.
- C.-H. Lee, S.-H. Hur, Y.-C. Shin, J.-H. Choi, D.-G. Park, and K. Kim, “Charge-trapping device structure of SiO2 SiNhigh-k dielectric Al2O3 for high-density flash memory,” Applied Physics Letters, vol. 86, no. 15, Article ID 152908, pp. 1–3, 2005.
- Y.-N. Tan, W.-K. Chim, B. J. Cho, and W.-K. Choi, “Over-erase phenomenon in SONOS-type flash memory and its minimization using a hafnium oxide charge storage layer,” IEEE Transactions on Electron Devices, vol. 51, no. 7, pp. 1143–1147, 2004.
- X. Wang, J. Liu, W. Bai, and D.-L. Kwong, “A novel MONOS-type nonvolatile memory using high-κ dielectrics for improved data retention and programming speed,” IEEE Transactions on Electron Devices, vol. 51, no. 4, pp. 597–602, 2004.
- X. Wang and D.-L. Kwong, “A novel high-k SONOS memory using TaN/Al2O3/Ta2O5/HfO2/Si structure for fast speed and long retention operation,” IEEE Transactions on Electron Devices, vol. 53, no. 1, pp. 78–82, 2006.
- S. Seki, T. Unagami, and B. Tsujiyama, “Electron trapping levels in rf-sputtered Ta2O5 films,” Journal of Vacuum Science and Technology A, vol. 1, no. 4, pp. 1825–1830, 1983.
- T.-M. Pan and W.-W. Yeh, “A high- k Y2O3 charge trapping layer for nonvolatile memory application,” Applied Physics Letters, vol. 92, no. 17, Article ID 173506, 2008.
- T.-M. Pan and W.-W. Yeh, “High-performance high-k Y2O3 SONOS-type flash memory,” IEEE Transactions on Electron Devices, vol. 55, no. 9, pp. 2354–2360, 2008.
- Y.-H. Lin, C.-H. Chien, C.-T. Lin, C.-Y. Chang, and T.-F. Lei, “Novel two-bit HfO2 nanocrystal nonvolatile flash memory,” IEEE Transactions on Electron Devices, vol. 53, no. 4, pp. 782–789, 2006.
- H.-C. You, T.-H. Hsu, F.-H. Ko, J.-W. Huang, and T.-F. Lei, “Hafnium silicate nanocrystal memory using sol-gel-spin-coating method,” IEEE Electron Device Letters, vol. 27, no. 8, pp. 644–646, 2006.
- T.-H. Hsu, H.-C. You, F.-H. Ko, and T.-F. Lei, “PolySi-SiO2-ZrO2-SiO2-Si flash memory incorporating a sol-gel-derived ZrO2 charge trapping layer,” Journal of the Electrochemical Society, vol. 153, no. 11, Article ID 030611JES, pp. G934–G937, 2006.
- Y.-H. Lin, C.-H. Chien, T.-Y. Yang, and T.-F. Lei, “Two-bit lanthanum oxide trapping layer nonvolatile flash memory,” Journal of the Electrochemical Society, vol. 154, no. 7, pp. H619–H622, 2007.
- F.-H. Chen, T.-M. Pan, and F.-C. Chiu, “Metal-oxide-high-k-oxide-silicon memory device using a Ti-doped Dy2O3 charge-trapping layer and Al2O3 blocking layer,” IEEE Transactions on Electron Devices, vol. 58, no. 11, pp. 3847–3851, 2011.