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Active and Passive Electronic Components
Volume 2011 (2011), Article ID 391642, 7 pages
http://dx.doi.org/10.1155/2011/391642
Research Article

Current Mode Biquad Filter with Minimum Component Count

Department of Electronics Engineering, Z. H. College of Engineering and Technology, AMU, Aligarh 202 002, India

Received 26 January 2011; Accepted 28 April 2011

Academic Editor: I. A. Khan

Copyright © 2011 Bhartendu Chaturvedi and Sudhanshu Maheshwari. This is an open access article distributed under the Creative Commons Attribution License, which permits unrestricted use, distribution, and reproduction in any medium, provided the original work is properly cited.

Abstract

The paper presents a new current mode biquadratic filter with one input and three outputs using differential voltage current conveyor (DVCC) and four passive components. The proposed circuit can simultaneously realize low-pass, band-pass, and high-pass filter functions without changing the circuit topology and passive elements. The circuit exhibits a good frequency performance and low-sensitivity figures. PSPICE simulation using 0.5 μm CMOS parameters are given to validate the proposed circuit. The circuit provides a simple yet novel solution to the current-mode filtering after appropriate incorporation of current sensing elements in form of current buffers.

1. Introduction

Current-mode circuits have been receiving considerable attention owing to their potential advantages such as wider bandwidth, greater linearity, higher slew rate, wider dynamic range, simple circuitry, and low power consumption compared to voltage-mode circuits [13]. Current-mode analog signal filtering has also received a lot of attention in the recent past. Thus, several multifunction or universal biquadratic filters using current conveyors have been reported in the literature [436]. Recently, CDTA has also been used for current-mode filtering application [5]. The circuit in [6] realizes three basic filtering functions and uses all grounded components. The circuit [7] is based on minimum number of passive elements. Another current mode work employs only one active element in the form of a CFOA [8]. One multifunction filter using two CDBAs was also reported [9]. Current mode filters [17] benefit from high output impedance and use of grounded components. An active element which also has merged as a potential candidate for realizing filter circuits is a differential voltage current conveyor [10, 11, 1719, 25, 26]. The works based on DVCC present a KHN biquad [10, 11] is benefiting from high output impedance outputs.

This paper presents a new second-order current mode filter circuit employing grounded components. The circuit uses a minimum number of components required to achieve a second-order transfer function. Three types of transfer functions are available at once, without any circuit modification. Moreover, the circuits using grounded components are beneficial from fabrication point of view. The non-ideal study and parasitic effects are also given. The new circuit is verified using PSPICE, a powerful tool for verifying new circuits based on active elements, which are either not commercially available or their implementation using available ICs is not very economical.

2. Proposed Circuit

2.1. Circuits’ Description

The symbol and CMOS implementation of differential voltage current conveyor (DVCC) are shown in Figures 1 and 2, respectively, and are characterized by the following port relationship:𝑉𝑋=𝑉𝑌1𝑉𝑌2,𝐼𝑌1=𝐼𝑌2=0,𝐼𝑍+=+𝐼𝑋.(1) A new current-mode biquadratic filter with one input terminal and three output terminals is proposed. The given circuit uses one differential voltage current conveyor (DVCC), two grounded resistors and two grounded capacitors. The given circuit can realize the standard filter functions: low-pass, band-pass, and high-pass, simultaneously without changing the passive elements. The given circuit uses one DVCC, two grounded resistors, and two grounded capacitors. The use of only grounded components is particularly attractive for IC implementation.

391642.fig.001
Figure 1: Symbol of DVCC with two Z+ stages.
391642.fig.002
Figure 2: CMOS implementation of DVCC with two Z+ stages.
2.2. Circuit Analysis

The proposed circuit of Figure 3 is analyzed using (1). The transfer functions can be expressed as𝐼LP𝐼in=1/𝐶1𝐶2𝑅1𝑅2𝑠2+𝑠1/𝐶2𝑅21/𝐶2𝑅1+1/𝐶1𝑅1+1/𝐶1𝐶2𝑅1𝑅2,𝐼BP𝐼in=𝑠/𝐶1𝑅1𝑠2+𝑠1/𝐶2𝑅21/𝐶2𝑅1+1/𝐶1𝑅1+1/𝐶1𝐶2𝑅1𝑅2,𝐼HP𝐼in=𝑠2+𝑠1/𝐶2𝑅21/𝐶2𝑅1𝑠2+𝑠1/𝐶2𝑅21/𝐶2𝑅1+1/𝐶1𝑅1+1/𝐶1𝐶2𝑅1𝑅2=𝑠2𝑠2+𝑠1/𝐶2𝑅+1/𝐶1𝐶2𝑅2for𝑅1=𝑅2.=𝑅(2) From (2), it can be seen that a low-pass response is obtained from 𝐼LP, a band-pass response is obtained from 𝐼BP, high-pass response is obtained from 𝐼HP under the condition 𝑅1=𝑅2=𝑅.

391642.fig.003
Figure 3: Proposed current-mode biquad filter.

In low-pass and band-pass responses, the resonance angular frequency 𝜔0 and the quality factor 𝑄 are given by𝜔0=1𝐶1𝐶2𝑅1𝑅2,𝑄=𝐶1𝐶2𝑅1𝑅2𝐶1𝑅1𝐶1𝑅2+𝐶2𝑅2.(3) It may be further noted that for high-pass response, the resistors are matched as 𝑅1=𝑅2=𝑅, so the resonance angular frequency 𝜔0 and the quality factor 𝑄 of the above (3) become𝜔0=1𝑅1𝐶1𝐶2,(4)𝑄=𝐶1𝐶2.(5) The high-pass gain, low-pass gain and band-pass gain, are given by 𝐻HP=1;𝐻LP=1;𝐻BP=𝑅2𝐶2𝑅2𝐶2+𝑅1𝐶1𝑅2𝐶1.(6) In (6), the high-pass gain and low-pass gain are in unity, and the band pass gain with equal resistor design also becomes unity. Sensitivity figures of the filter parameters (3) for the proposed circuit is analyzed. Pole frequency sensitivity is found to be 0.5 in magnitude for all elements 𝑆𝜔0𝑅1=𝑆𝜔0𝑅2=𝑆𝜔0𝐶1=𝑆𝜔0𝐶21=2.(7) Pole-𝑄 sensitivity for resistive and capacitive elements is, respectively, found as𝑆𝑄𝑅1=𝐶2𝑅2𝐶1𝑅2𝐶1𝑅12𝐶2𝑅2+𝐶1𝑅1𝐶1𝑅2,𝑆𝑄𝑅2=𝐶1𝑅2+𝐶1𝑅1𝐶2𝑅22𝐶2𝑅2+𝐶1𝑅1𝐶1𝑅2,𝑆𝑄𝐶1=𝐶1𝑅2+𝐶2𝑅2𝐶1𝑅12𝐶2𝑅2+𝐶1𝑅1𝐶1𝑅2,𝑆𝑄𝐶2=𝐶1𝑅1𝐶2𝑅2𝐶1𝑅22𝐶2𝑅2+𝐶1𝑅1𝐶1𝑅2.(8) For equal capacitor and resistor design, the sensitivity of pole-𝑄 to resistive and capacitive elements becomes less than unity in magnitude. It is to be noted that a new active element,namely, current backward transconductance Amplifier (CBTA), has been recently used for current and voltage mode filtering applications [33]. The recent work includes current mode universal filter with single input and three outputs using single active element and only grounded passive components. The circuit also enjoys low active and passive sensitivities. The novel CBTA-based work employs as many as 22 transistors along with a floating current source, which is cumbersome to implement, as compared to the proposed circuit which uses only 10 transistors and no current source. Therefore, the new proposed circuit is lot simpler than the recent novel work [33].

3. Nonidealities and Parasitic Study

3.1. Nonideal Analysis

Taking the tracking errors of the DVCC into account, the relationship of the terminal voltages and currents of the DVCC can be rewritten as𝑉𝑋=𝛽1𝑉𝑌1𝛽2𝑉𝑌2,𝐼𝑌1=𝐼𝑌2𝐼=0,𝑍1+=+𝛼1𝐼𝑋,𝐼𝑍2+=+𝛼2𝐼𝑋.(9) Here, 𝛽1 and 𝛽2 are the voltage transfer gains from 𝑌1 and 𝑌2 terminal, respectively, to the 𝑋 terminal and 𝛼1 is the current transfer gain of DVCC from 𝑋 to 𝑍1+ terminal, 𝛼2 is the current transfer gain of DVCC from the 𝑋 to 𝑍2+ terminal. The above transfer gains deviate unity by the voltage and current transfer errors, which are quite small and technology dependent. Moreover, the transfer gains, instead of being real, are actually frequency dependent with an upper bound on the usable frequency.

The current mode biquad filter of Figure 3 is analyzed using (9) (nonideal characteristic equations), thus transfer functions become as 𝐼LP𝐼in𝛼=1𝛽2𝐶1𝐶2𝑅1𝑅2𝑠21+𝑠𝐶2𝑅2𝛼1𝛽1𝐶2𝑅1+𝛼2𝛽2𝐶1𝑅1+𝛼2𝛽2𝐶1𝐶2𝑅1𝑅2,𝐼BP𝐼in=𝑠𝛼1𝛽2𝐶1𝑅1𝑠21+𝑠𝐶2𝑅2𝛼1𝛽1𝐶2𝑅1+𝛼2𝛽2𝐶1𝑅1+𝛼2𝛽2𝐶1𝐶2𝑅1𝑅2,𝐼HP𝐼in=𝑠21+𝑠𝐶2𝑅2𝛼1𝛽1𝐶2𝑅1𝑠21+𝑠𝐶2𝑅2𝛼1𝛽1𝐶2𝑅1+𝛼2𝛽2𝐶1𝑅1+𝛼2𝛽2𝐶1𝐶2𝑅1𝑅2,(10) where 𝛽1 and 𝛽2 are the voltage transfer gains of DVCC from the 𝑌1 and 𝑌2 terminals to the 𝑋 terminal, respectively, 𝛼1 is the current transferw gain of DVCC from 𝑋 to 𝑍1+ terminal, 𝛼2 is the current transfer gain of DVCC from the 𝑋 to 𝑍2+ terminal. Equation (10) show the transfer function of second order low-pass filter, band-pass filter, and high pass filter with nonidealities of DVCC, respectively. And it is to be noted that (10) reduces to (2) for 𝛼𝑗=𝛽𝑗=1 (where 𝑗=1,2).

The resonance angular frequency 𝜔0 and quality factor 𝑄 with non idealities are obtained by𝜔0=𝛼2𝛽2𝐶1𝐶2𝑅1𝑅2,(11)𝑄=𝛼2𝛽2𝐶1𝐶2𝑅1𝑅2𝐶1𝑅1𝛼1𝛽1𝐶1𝑅2+𝛼2𝛽2𝐶2𝑅2,(12) where 𝛽1 and 𝛽2 are the voltage transfer gains of DVCC from the 𝑌1 and 𝑌2 terminals to the 𝑋 terminal, respectively, 𝛼1 is the current transfer gain of DVCC from 𝑋 to 𝑍1+ terminal, 𝛼2 is the current transfer gain of DVCC from the 𝑋 to 𝑍2+ terminal. It is to be further noted that (11) reduces to (4) and (12) reduces to (5) for 𝛼𝑗=𝛽𝑗=1 (where 𝑗=1,2).

The active and passive pole frequency sensitivity is found to be 0.5 in magnitude for all elements𝑆𝜔0𝛼2=𝑆𝜔0𝛽2=𝑆𝜔0𝑅1=𝑆𝜔0𝑅2=𝑆𝜔0𝐶1=𝑆𝜔0𝐶2=12.(13) Pole-𝑄 sensitivity for active and passive elements is found as𝑆𝑄𝑅1=12𝛼2𝛽2𝐶2𝑅2𝛼1𝛽1𝐶1𝑅2𝐶1𝑅1𝛼2𝛽2𝐶2𝑅2+𝐶1𝑅1𝛼1𝛽1𝐶1𝑅2,𝑆𝑄𝑅2=12𝛼1𝛽1𝐶1𝑅2𝛼2𝛽2𝐶2𝑅2+𝐶1𝑅1𝛼2𝛽2𝐶2𝑅2+𝐶1𝑅1𝛼1𝛽1𝐶1𝑅2,𝑆𝑄𝐶1=12𝛼2𝛽2𝐶2𝑅2+𝛼1𝛽1𝐶1𝑅2𝐶1𝑅1𝛼2𝛽2𝐶2𝑅2+𝐶1𝑅1𝛼1𝛽1𝐶1𝑅2,𝑆𝑄𝐶2=12𝐶1𝑅1𝛼2𝛽2𝐶2𝑅2𝛼1𝛽1𝐶1𝑅2𝛼2𝛽2𝐶2𝑅2+𝐶1𝑅1𝛼1𝛽1𝐶1𝑅2,𝑆𝑄𝛼1=𝑆𝑄𝛽1=𝛼1𝛽1𝐶1𝑅2𝛼2𝛽2𝐶2𝑅2+𝐶1𝑅1𝛼1𝛽1𝐶1𝑅2,𝑆𝑄𝛼2=𝑆𝑄𝛽2=12𝐶1𝑅1𝛼2𝛽2𝐶2𝑅2𝛼1𝛽1𝐶1𝑅2𝛼2𝛽2𝐶2𝑅2+𝐶1𝑅1𝛼1𝛽1𝐶1𝑅2,(14) where 𝛽1 and 𝛽2 are the voltage transfer gains of DVCC from the 𝑌1 and 𝑌2 terminals to the 𝑋 terminal, respectively, 𝛼1 is the current transfer gain of DVCC from 𝑋 to 𝑍1+ terminal, and 𝛼2 is the current transfer gain of DVCC from the 𝑋 to 𝑍2+ terminal. For equal capacitor and resistor design, the sensitivity of pole-𝑄 to active and passive elements becomes within unity in magnitude.

3.2. Effect of DVCC Parasitics

Analogous to the second-generation current conveyor (CCII), the DVCC has a small parasitic resistance 𝑅𝑋 at port 𝑋 and high output impedance (𝑅𝑧//𝐶𝑧) at port 𝑍. As the 𝑋 terminal of the DVCC is connected to a resistor, the parasitic resistance at the 𝑋 terminal of the DVCC (𝑅𝑋) can be absorbed as a part of the main resistance. As the value of 𝑅𝑋1 is much smaller, then the external resistor (𝑅1), so pole-ωo of the proposed circuit of second-order current mode biquad filter will not be affected. The effects of the capacitors at port 𝑌 and 𝑍 of the DVCC are also negligible, because these capacitors are quite small (and process dependent) as compared to the external capacitors. However, the effective values of the capacitors after parasitics’ inclusion is given below: 𝐶1(eective)=𝐶1+𝐶𝑍2++𝐶𝑌2,𝐶2(eective)=𝐶2+𝐶𝑌1+𝐶𝑍1+.(15)

From (15), it is clear that the parasitic capacitances appear in shunt with external capacitors thus ensuring a possibility of predistorting the designed values. Therefore, it is to be concluded that the circuits are not adversely affected by the parasitic capacitances and 𝑋-terminal resistances. This would be further confirmed in the following section.

3.3. Output Current Sensing

It may next be argued that the output currents are through passive elements. Moreover, the impedance level may also not be desirable and even frequency dependent (where the output is through a capacitor). Additional current sensing elements in form of current followers can be employed for the purpose. It is a well known fact that current conveyor itself can be used to realize an accurate current follower. This would then ensure high impedance current output but at the cost of un-grounding the passive components. All these issues are quite obvious, but keeping in view the simplicity of the proposed circuit topology, this may not be seen as a drawback of the proposed work. Other available work also suffers from similar current sensing problems [32] as compared to many others which actually show high impedance output filter functions [17, 30, 34]. As already pointed out, the current follower is easily realized using a DVCC itself, by utilizing 𝑋 and 𝑍 as input and outputs, respectively (grounding 𝑌 terminals). The current follower circuit is shown in Figure 4 for completeness sake. Figure 4(a) realizes a positive current follower, whereas Figure 4(b) realizes a negative (inverting) current follower. The use of current follower would make the passive elements virtually grounded instead of being physically grounded.

fig4
Figure 4: Circuit of current follower using DVCC (a) Inverting (b) Noninverting.

4. Simulation Results

PSPICE simulations were performed using the CMOS realization of DVCC with 0.5 μ level 3 MOSFET parameters as also listed in Algorithm 1 and Table 1. The supply voltages used were ±2.5 V and 𝑉BB= −1.6 V. The proposed circuit of second-order current mode biquad filter (Figure 3) circuit was designed with 𝑄=1, 𝑓𝑜=9.7 MHz: 𝐶1 = 𝐶2 = 10 pF, 𝑅1 = 𝑅2 = 2 KΩ. The simulated resonance frequency is same as designed one. The power consumption was found to be 4.9 mW. The simulation results of second-order current-mode biquad are shown in from Figure 5 to Figure 9. Figure 5 shows the simulated gain plots of all three responses (high-pass response, low-pass response, and band-pass response). Figure 6 shows the simulated transient output for low-pass with amplitude of 140 μA peak to peak at input of 9.7 MHz. Figure 7 shows the simulated transient output for band-pass with amplitude of 180 μA peak to peak at input of 9.7 MHz. Figure 8 shows the simulated transient output for high-pass with amplitude of 240 μA peak to peak at input of 9.7 MHz. The output waveform for high-pass function at 1 GHz frequency is also shown in Figure 9. As it can be seen, there is a close agreement between the theory and the simulation. The T.H.D. of the proposed circuit at all outputs is within 2%, which is low, keeping in view the frequency of operation.

tab1
Table 1: Aspect ratios used.

alg1
Algorithm 1: Model parameters used for simulation.

391642.fig.005
Figure 5: Gain plot in dB showing all three responses.
391642.fig.006
Figure 6: Low pass output for sinusoidal input of 9.7 MHz.
391642.fig.007
Figure 7: Band pass output for sinusoidal input of 9.7 MHz.
391642.fig.008
Figure 8: High-pass output for sinusoidal input of 9.7 MHz
391642.fig.009
Figure 9: High-pass output at 1 GHz.

5. Conclusion

A new second-order current-mode active filter is presented. It is very simple and contains a minimum number of components required to achieve a second-order transfer function. Three types of transfer functions are available at once, without any circuit modification. However, due to the circuit simplicity, 𝑓𝑜 and 𝑄 are not independently adjustable. The new circuit is suited for high-frequency operation. PSPICE simulations using 0.5 μm CMOS parameters support the validity and practical utility of the proposed circuit.

Acknowledgment

The authors are thankful to the Editor Professor Iqbal A. Khan for getting the paper promptly reviewed and for recommending this paper.

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