Novel Power Reduction Technique for ReRAM with Automatic Avoidance Circuit for Wasteful Overwrite

Figure 12

Concept of power reduction using automatic avoidance circuit against conventional nonavoidance scheme.

(a) SL and BL voltage w/o avoidance

(b) SL and BL voltage w/avoidance

(c) Current flows through ReRAM w/o avoidance

(d) Current flows through ReRAM w/o avoidance

(e) Power consumed in ReRAM w/o avoidance

(f) Power consumed in ReRAM w/avoidance