181395.fig.0012a
(a) SL and BL voltage w/o avoidance
181395.fig.0012b
(b) SL and BL voltage w/avoidance
181395.fig.0012c
(c) Current flows through ReRAM w/o avoidance
181395.fig.0012d
(d) Current flows through ReRAM w/o avoidance
181395.fig.0012e
(e) Power consumed in ReRAM w/o avoidance
181395.fig.0012f
(f) Power consumed in ReRAM w/avoidance
Figure 12: Concept of power reduction using automatic avoidance circuit against conventional nonavoidance scheme.