Table 1: Differential output voltages of the proposed D-latch for various input combinations.

Differential inputsPresent stateCurrents through the transistorsNext state differential output (
CLKD Q M LV3M LV4M LV5M LV6M LV7M LV8Level

LLL 0 0 0
LLH 00 0
LHL0 0 0
LHH0 0 0
HLL 0 00
HLH 00 0
HHL0 00
HHH0 0 0

= low/high differential input voltage, , , and .