About this Journal Submit a Manuscript Table of Contents
Active and Passive Electronic Components
Volume 2013 (2013), Article ID 217674, 9 pages
http://dx.doi.org/10.1155/2013/217674
Research Article

MCML D-Latch Using Triple-Tail Cells: Analysis and Design

1Electronics and Communication Division, Delhi Technological University, Delhi 110042, India
2Electronics and Communication Division, Netaji Subhas Institute of Technology, Delhi 110078, India

Received 25 June 2013; Accepted 17 September 2013

Academic Editor: Ching Liang Dai

Copyright © 2013 Kirti Gupta et al. This is an open access article distributed under the Creative Commons Attribution License, which permits unrestricted use, distribution, and reproduction in any medium, provided the original work is properly cited.

Abstract

A new low-voltage MOS current mode logic (MCML) topology for D-latch is proposed. The new topology employs a triple-tail cell to lower the supply voltage requirement in comparison to traditional MCML D-latch. The design of the proposed MCML D-latch is carried out through analytical modeling of its static parameters. The delay is expressed in terms of the bias current and the voltage swing so that it can be traded off with the power consumption. The proposed low-voltage MCML D-latch is analyzed for the two design cases, namely, high-speed and power-efficient, and the performance is compared with the traditional MCML D-latch for each design case. The theoretical propositions are validated through extensive SPICE simulations using TSMC 0.18 µm CMOS technology parameters.

1. Introduction

The advances in semiconductor technology have led to the integration of high performance digital and analog circuits on the same silicon substrate. The traditional CMOS logic style does not provide an analog friendly environment due to the large switching noise [13]. Many alternate logic styles have been suggested in [36] and the reference mentioned therein. MOS current mode logic (MCML) style is the most promising one due to the lower switching noise in comparison to traditional CMOS logic style [69]. Also, it exhibits better power delay than the traditional CMOS logic style at high frequencies [615]. Therefore, MCML style is appropriate for designing high performance digital circuits wherein a D-latch is widely used as a building block in different applications such as prescalars, frequency dividers, and sequential logic circuits [1620].

The D-latch topology given in [1620] is referred to as traditional D-latch and is based on the series-gating approach (i.e., stacked source-coupled transistor pairs) [9] which puts a limit on the minimum power supply. The power supply may, however, be lowered by reducing the number of stacked transistor pair levels with triple-tail cell concept [2123]. In this paper, a new low-voltage MCML D-latch is proposed. The static parameters for the proposed D-latch are analytically modeled and applied to develop a design approach. From the knowledge of the transistor sizes, the delay is expressed in terms of the bias current and the voltage swing so that it can be traded off with the power consumption. The proposed low-voltage multiplexer is analyzed for high-speed and power-efficient design cases. A comparison in performance of the proposed D-latch with the traditional one is carried out for all the cases.

The paper first briefs the operation of the traditional MCML D-latch in Section 2. Thereafter, a new low-voltage MCML topology for the D-latch is proposed, and analytical formulations for different static parameters and delay are put forward in Section 3. The analysis of the proposed D-latch for the different design cases is presented, and its performance is compared with the traditional one in Section 4. Extensive SPICE simulations are carried out to validate the proposed theory. Section 5 concludes the paper.

2. Traditional MCML D-Latch

A traditional MCML D-latch with differential inputs and CLK is shown in Figure 1 [24]. It consists of two levels of source-coupled transistor pairs to implement the logic function and a constant current source to generate bias current . The differential input CLK drives the lower level transistor pair - that alternatively activates the upper level transistor pairs - and -. When differential input CLK is high, is OFF and the bias current flows through and is steered either to or according to the differential input to ensure that the D-latch operates in the transparent state. Conversely, when the differential input CLK is low, the bias current flows through and is steered to one of the two transistors, that is, either or according to the previous output value such that the output does not respond to the changes in the input; thus, D-latch remains in the hold state. The bias current is converted to the differential output voltage () through the PMOS transistors and [24]. The load capacitance includes the effect of fanout and the interconnect capacitances.

217674.fig.001
Figure 1: Traditional MCML D-latch.

The minimum supply voltage, , for the traditional D-latch is defined as the lowest voltage at which all the transistors in the two levels and the current source operate in the saturation region [25] and is computed as where is the threshold voltage of the transistors , is the threshold voltage of , and is the biasing voltage of .

3. Proposed Low-Voltage MCML D-Latch

The proposed low-voltage D-latch with differential inputs and CLK is shown in Figure 2. It consists of two triple-tail cells (, , ) and (, , ) biased by separate current sources of /2 value. The transistors and are driven by the differential CLK input and are connected between the supply terminal and the common source terminal of transistor pairs - and -, respectively. A high differential CLK voltage turns ON the transistor , and deactivates the transistor pair -. At the same time, the transistor turns OFF so that the transistor pair - generates the output according to the differential input . Thus, the D-latch works in the transparent state. Similarly, the transistor pair - gets activated for low differential CLK voltage and preserves the previous output. Therefore the D-latch operates in the hold state for low value of the differential CLK input.

217674.fig.002
Figure 2: Proposed low-voltage D-latch.

The minimum supply voltage, , for the proposed D-latch is computed by the method outlined in [25] as where is the threshold voltage of transistor , is the threshold voltage of , and is the biasing voltage of .

3.1. Static Model

The static model is derived by modeling the load transistors , by an equivalent linear resistance, [26]. Using the standard BSIM3v3 model, the linear resistance, is computed as where is the empirical model parameter, the channel width of the load transistor, and the parameter is the intrinsic resistance of the PMOS transistor in the linear region and is given as where is the oxide capacitance per unit area. The parameters , and are the effective hole mobility, the threshold voltage, and the effective channel length of the load transistor, respectively.

It may be noted that if equal aspect ratio of all transistors in the triple-tail cells is considered, then the transistors and will not be able to completely switch OFF the transistor pair - and -. Hence, for proper operation, the aspect ratio of transistors , is made greater than the other transistors’ aspect ratio by a factor . As an example if the value of differential input is chosen such that the transistors , are ON while the transistors , are OFF, then a high differential CLK voltage turns ON the transistor . But since the transistors and have the same gate-source voltages, the currents flowing through () and () can be written asThe current through can be minimized by increasing factor . This input condition produces minimum output voltage as where , and are the currents through transistors , , , and , respectively. The differential output voltages for various input combinations are enlisted in Table 1. It can be observed from Table 1 that there are two values of maximum output voltage () and minimum output voltage () for different input and output combinations. Consequently, the voltage swing, , when the input and output are the same can be expressed as where are maximum output voltage and minimum output voltage, respectively, for the same input/output. The voltage swing, , when the input and output are different can be expressed as where are maximum output voltage and minimum output voltage, respectively, for different input/output.

tab1
Table 1: Differential output voltages of the proposed D-latch for various input combinations.

As , has been considered as the worst case voltage swing: The small-signal voltage gain ( and noise margin (NM) for the proposed D-latch are computed by the method outlined in [26] as where , , , and are the effective electron mobility, the transconductance, the effective channel width, and length of transistors , respectively.

3.2. Transistor Sizing

In this section, an approach to size the transistors of the proposed low-voltage D-latch on the basis of static model is developed.

For a specified value of NM, factor , and (1.4 for MCML [8]), the voltage swing of the proposed D-latch is calculated using (10) as It may be noted that should be lower than the maximum value of so as to ensure that transistors operate in saturation region. The voltage swing obtained from (11) requires sizing of the load transistor with equivalent resistance . To this end, the equivalent resistance, , for the minimum sized PMOS transistor is first determined, and then the bias current for the required voltage swing is determined as If the bias current is higher than , then should be less than , and this is achieved by setting to its minimum value, that is, and which is calculated by solving (3) and (4) as Similarly, if the bias current is lower than , then should be greater than , and this is achieved by setting to its minimum value, that is, and which is calculated by solving (3) and (4) as The small-signal voltage gain (9) has been used to size transistors . Assuming minimum channel length for the said transistors, the width is computed as Sometimes (15) results in a value of smaller than the minimum channel width. This happens when the bias current is lower than the current of the minimum sized NMOS transistor, , given as Therefore, in such cases, is also set to . For proper switching, the width of transistors is made times the width of transistors .

The accuracy of the static model for the proposed D-latch is validated through SPICE simulations by using TSMC 0.18 μm CMOS process parameters and with a power supply of 1.1 V. The proposed D-latch was designed and simulated for wide range of operating conditions: voltage swing of 300 mV and 400 mV, small-signal voltage gain of 2 and 4, , and the bias current ranging from 10 μA to 100 μA. The designs were simulated, and the error in simulated and theoretical values for voltage swing, small-signal voltage gain, and noise margin using (8), (9), and (10), respectively, are calculated and are plotted in Figure 3. It may be noted that maximum error in voltage swing, small-signal voltage gain, and noise margin are 10%, 8%, and 14%, respectively.

fig3
Figure 3: Errors in the static parameters (a) voltage swing, (b) small-signal voltage gain, and (c) noise margin.

The impact of parameter variation on proposed low-voltage and traditional MCML D-latch performance is studied at different design corners. The findings for various operating conditions are given in Table 2. It is found that the voltage swing, small-signal voltage gain, and noise margin of the proposed low-voltage D-latch varies by a factor of 1.8, 1.4, and 2.1, respectively, between the best and the worst cases. For the traditional MCML D-latch, the voltage swing, small-signal voltage gain, and noise margin vary by a factor of 1.7, 1.2, and 1.7, respectively, between the best and the worst cases. Thus, the proposed low-voltage D-latch shows slightly higher variations than those of the traditional MCML D-latch for different design corners which can be attributed to the smaller aspect ratio of transistors in the proposed low-voltage D-latch [8].

tab2
Table 2: Effect of process variation on static parameters of the proposed and the traditional D-latch.
3.3. Delay Model

In this section, a delay model of the proposed D-latch is formulated in terms of bias current and the voltage swing. For a low-to-high transition on CLK input that causes output to switch by activating (deactivating) the transistor pair - (-), the circuit reduces to a simple MCML inverter. The equivalent linear half circuit is shown in Figure 4 where represent the gate-drain capacitance and the drain-bulk junction capacitance of the th transistor. For NMOS transistors operating in saturation region, is equal to the overlap capacitance between the gate and the drain [26]. For the PMOS transistor operating in linear region, is evaluated as the sum of the overlap capacitance and the intrinsic contribution associated with its channel charge [26]. The junction capacitance for the transistors is computed as explained in [27]. The input capacitance represents the input capacitance of the source-coupled pair (-) [9].

217674.fig.004
Figure 4: Linear half circuit (with low-to-high transition on CLK).

The delay of the proposed D-latch can be expressed as with , and, ; (17) can be rewritten as The capacitances may be expressed in terms of the bias current and the voltage swing as where is the capacitance between the terminals and and , , and are the associated coefficients. Using (14) and (15), various capacitances in (18) for ranging from to may be expressed as where is the drain-gate overlap capacitance per unit transistor width. Consider the following: where , are the zero-bias junction capacitance per unit area and zero-bias sidewall capacitance per unit parameter, respectively. The coefficients , are the voltage equivalence factor for the junction and the sidewall capacitances [27]. Parameter is extrapolated from design rules [9]. Consider the following: where is a parameter defined in BSIM3v3 model [24]. Consider the following: where , are the zero-bias junction capacitance per unit area and zero-bias sidewall capacitance per unit parameter respectively. The coefficients , are the voltage equivalence factor for the junction and the sidewall capacitances of the PMOS transistor, respectively [27]. Parameter is extrapolated from design rules [9]. The coefficients , and of all the capacitances in (18) are summarized in Table 3. Using (20)–(24), (18) can be written as whereThe delay model can also be used for value outside the range [, ]. This is because for , the capacitance coefficients of PMOS transistor in (25) differ as explained in Section 3.2. But since for high values of , the capacitive contribution of PMOS transistor is negligible, therefore (25) can predict the delay. Similarly, for , the capacitance coefficients of NMOS transistor in (25) differ. But since for low values of , the delay majorly depends on the capacitances of PMOS transistor, so expression (25) can estimate the delay of the proposed D-latch.

tab3
Table 3: Coefficients of the capacitances for the proposed D-latch.

The accuracy of the delay model for the proposed D-latch is validated through SPICE simulations by using TSMC 0.18 μm CMOS process parameters and with a power supply of 1.1 V. The proposed D-latch was designed for wide range of operating conditions: voltage swing of 300 mV and 400 mV, small-signal voltage gain of 2 and 4, the bias current ranging from 10 μA to 100 μA, , and load capacitance of 0 fF, 10 fF, 100 fF, and 1 pF. It is found that there is a close agreement between the simulated and the predicted delay for all the operating conditions. The simulated and the predicted delay in particular for NM = 130 mV and and with different load capacitances are plotted in Figure 5.

fig5
Figure 5: Simulated and predicted delay of proposed D-latch versus with NM = 130 mV, , and different load capacitances (a)  fF, (b)  fF, (c)  fF, and (d)  pF.

The impact of parameter variation on proposed low-voltage and traditional MCML D-latches delay is studied at different design corners. The findings for various operating conditions are given in Table 4. It is found that the propagation delay of the proposed low-voltage D-latch varies by a factor of 1.8 between the best and the worst cases. For the traditional MCML D-latch, the delay varies by a factor of 1.7 between the best and the worst cases. Thus, the proposed low-voltage D-latch shows slightly higher variation than the traditional MCML D-latch in delay for different design corners which can be attributed to the smaller aspect ratio of transistors in the proposed low-voltage D-latch [8].

tab4
Table 4: Effect of process variation on the delay of the proposed and the traditional D-latch.

4. Design Cases

In the previous section, the proposed D-latch has been modeled, and different parameters are expressed as a function of bias current and voltage swing. In practice, the voltage swing is set on the basis of the specified noise margin while the bias current is chosen according to power-delay considerations. Therefore, the proposed low-voltage D-latch for high-speed and power-efficient design cases is discussed.

4.1. High-Speed Design

A high-speed design requires bias current that results in minimum delay. The delay (25) decreases with the increasing and tends to an asymptotic minimum value of for ∞. A substantial improvement in delay with increasing bias current is achieved if condition is satisfied. However, high value of bias current results in large transistor sizes. Therefore, the bias current should be set to such a value after which the improvement in speed is not significant. If equality sign in (27) is considered, then the delay is close to its minimum value, and the use of high bias current is avoided. Therefore, this assumption leads to a bias current ( and delay as The proposed high-speed D-latch, designed with a power supply of 1.1 V, noise margin of 130 mV, small-signal gain of 4, , and load capacitance of 100 fF, gives as 254 μA. A delay of 265 ps and 255 ps is obtained from (29) and simulations, respectively. On the contrary, a traditional high-speed D-latch designed using the method outlined in [24] and with power supply of 1.4 V for the same specifications results in a delay of 598 ps. This indicates that the proposed D-latch can achieve a much higher speed than the traditional one.

4.2. Power-Efficient Design

A power-efficient design requires a bias current that results in minimum power-delay product (PDP). The power is calculated as the product of and . So, the PDP of the proposed D-latch may be expressed as Therefore, the current for minimum PDP may be given as Accordingly, the minimum PDP results in The proposed power-efficient D-latch, designed with a power supply of 1.1 V, noise margin of 130 mV, small signal gain of 4, , and load capacitance of 100 fF, gives as 5.3 μA. A PDP value of 38.5 fJ has been obtained for the proposed D-latch. On the other hand, a traditional power-efficient D-latch designed using the method outlined in [24] and with power supply of 1.4 V for the same specifications results in a PDP value of 24 fJ. The result signifies that the proposed D-latch results in higher PDP values than the traditional one.

5. Conclusions

A new low-voltage MCML D-latch based on the triple-tail cell concept is proposed. Its static parameters are analytically modeled and are used to develop a design approach for the proposed low-voltage MCML D-latch. The delay is formulated as a function of the bias current and the voltage swing and is traded off with power consumption for high-speed and power-efficient design cases. It is found that the proposed low-voltage D-latch is better than those of the traditional MCML D-latch for the high-speed design case.

References

  1. S. Kiaei and D. Allstot, “Low-noise logic for mixed-mode VLSI circuits,” Microelectronics Journal, vol. 23, no. 2, pp. 103–114, 1992. View at Scopus
  2. M. Anis, M. Allam, and M. Elmasry, “Impact of technology scaling on CMOS logic styles,” IEEE Transactions on Circuits and Systems II, vol. 49, no. 8, pp. 577–589, 2002.
  3. M. Alioto and G. Palumbo, “Design strategies for source coupled logic,” IEEE Transactions on Circuits and Systems I, vol. 50, no. 5, pp. 640–654, 2003.
  4. N. H. E. Weste, D. Harris, and A. Banerjee, CMOS VLSI Design: A Circuits and System Perspective, Pearson Education, New York, NY, USA, 4th edition, 2010.
  5. J. Kundan and S. M. Hasan, “Enhanced folded source-coupled logic technique for low-voltage mixed-signal integrated circuits,” IEEE Transactions on Circuits and Systems II, vol. 47, no. 8, pp. 810–817, 2000. View at Publisher · View at Google Scholar · View at Scopus
  6. J. M. Musicer and J. Rabaey, “MOS current mode logic for low power, low noise CORDIC computation in mixed-signal environments,” in Proceedings of the International Symposium on Low Power Electronics and Design (ISLPED '00), pp. 102–107, July 2000. View at Scopus
  7. S. Bruma, “Impact of on-chip process variations on MCML performance,” in Proceedings of the IEEE International Systems-on-Chip Conference, pp. 135–140, September 2003. View at Publisher · View at Google Scholar
  8. H. Hassan, M. Anis, and M. Elmasry, “MOS current mode circuits: analysis, design, and variability,” IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol. 13, no. 8, pp. 885–898, 2005. View at Publisher · View at Google Scholar · View at Scopus
  9. M. Alioto and G. Palumbo, Model and Design of Bipolar and MOS Current-Mode Logic (CML, ECL and SCL Digital Circuits), Springer, New York, NY, USA, 2005.
  10. G. Caruso and A. Macchiarella, “A methodology for the design of MOS current-mode logic circuits,” IEICE Transactions on Electronics, vol. 93, no. 2, pp. 172–181, 2010. View at Publisher · View at Google Scholar · View at Scopus
  11. M. Alioto and G. Palumbo, “Power-aware design of nanometer MCML tapered buffers,” IEEE Transactions on Circuits and Systems II, vol. 55, no. 1, pp. 16–20, 2008. View at Publisher · View at Google Scholar · View at Scopus
  12. G. Caruso, “Power-aware design of MCML logarithmic adders,” in Proceedings of the International Conference on Signals and Electronic Systems (ICSES '10), pp. 281–283, September 2010.
  13. Y. M. El-Hariry and A. H. Madian, “MOS current mode logic realization of digital arithmetic circuits,” in Proceedings of the International Conference on Microelectronics (ICM '10), pp. 128–131, Cairo, Egypt, December 2010. View at Publisher · View at Google Scholar · View at Scopus
  14. O. Musa and M. Shams, “An efficient delay model for MOS current-mode logic automated design and optimization,” IEEE Transactions on Circuits and Systems I, vol. 57, no. 8, pp. 2041–2052, 2010. View at Publisher · View at Google Scholar · View at Scopus
  15. A. Cevrero, F. Regazzoni, M. Schwander, S. Badel, P. Ienne, and Y. Leblebici, “Power-gated MOS current mode logic (PG-MCML): a power aware DPA-resistant standard cell library,” in Proceedings of the 48th ACM/EDAC/IEEE Design Automation Conference (DAC '11), pp. 1014–1019, San Diego, Calif, USA, June 2011. View at Scopus
  16. M. Alioto, R. Mita, and G. Palumbo, “Design of high-speed power-efficient MOS current-mode logic frequency dividers,” IEEE Transactions on Circuits and Systems II, vol. 53, no. 11, pp. 1165–1169, 2006. View at Publisher · View at Google Scholar · View at Scopus
  17. R. Nonis, E. Palumbo, P. Palestri, and L. Selmi, “A design methodology for MOS current-mode logic frequency dividers,” IEEE Transactions on Circuits and Systems II, vol. 54, no. 2, pp. 245–254, 2007. View at Publisher · View at Google Scholar · View at Scopus
  18. J. K. Shin, T. W. Yoo, and M. S. Lee, “Design of half-rate linear phase detector using MOS current-mode logic gates for 10-Gb/s clock and data recovery circuit,” in Proceedings of the 7th International Conference on Advanced Communication Technology (ICACT '05), pp. 205–212, February 2005. View at Scopus
  19. C. Zhou, L. Zhang, H. Wang et al., “A 1 mW power-efficient high frequency CML 2:1 divider,” Analog Integrated Circuits and Signal Processing, vol. 71, no. 3, pp. 515–523, 2012.
  20. S. B. Anand and B. Razavi, “A CMOS clock recovery circuit for 2.5-Gb/s NRZ data,” IEEE Journal of Solid-State Circuits, vol. 36, no. 3, pp. 432–439, 2001. View at Publisher · View at Google Scholar · View at Scopus
  21. K. Gupta, N. Pandey, and M. Gupta, “Low-voltage MOS current mode logic multiplexer,” Radioengineering Journal, vol. 22, pp. 259–268, 2013.
  22. K. Gupta, N. Pandey, and M. Gupta, “Analysis and design of MOS current mode logic exclusive-OR gate using triple-tail cells,” Microelectronics Journal, vol. 44, no. 6, pp. 561–567, 2013. View at Publisher · View at Google Scholar
  23. M. Alioto, R. Mita, and G. Palumbo, “Performance evaluation of the low-voltage CML D-latch topology,” Integration, vol. 36, no. 4, pp. 191–209, 2003. View at Publisher · View at Google Scholar · View at Scopus
  24. M. Alioto and G. Palumbo, “Power-delay optimization of D-latch/MUX source coupled logic gates,” International Journal of Circuit Theory and Applications, vol. 33, no. 1, pp. 65–86, 2005. View at Publisher · View at Google Scholar · View at Scopus
  25. H. Hassan, M. Anis, and M. Elmasry, “Low-power multi-threshold MCML: analysis, design, and variability,” Microelectronics Journal, vol. 37, no. 10, pp. 1097–1104, 2006. View at Publisher · View at Google Scholar · View at Scopus
  26. M. Alioto, G. Palumbo, and S. Pennisi, “Modelling of source-coupled logic gates,” International Journal of Circuit Theory and Applications, vol. 30, no. 4, pp. 459–477, 2002. View at Publisher · View at Google Scholar · View at Scopus
  27. J. Rabaey, Digital Integrated Circuits: A Design Perspective, Prentice-Hall, Englewood Cliffs, NJ, USA, 4th edition, 2009.