- About this Journal ·
- Abstracting and Indexing ·
- Aims and Scope ·
- Article Processing Charges ·
- Author Guidelines ·
- Bibliographic Information ·
- Citations to this Journal ·
- Contact Information ·
- Editorial Board ·
- Editorial Workflow ·
- Free eTOC Alerts ·
- Publication Ethics ·
- Recently Accepted Articles ·
- Reviewers Acknowledgment ·
- Submit a Manuscript ·
- Subscription Information ·
- Table of Contents
Active and Passive Electronic Components
Volume 2013 (2013), Article ID 839198, 9 pages
Circuit Implementation, Operation, and Simulation of Multivalued Nonvolatile Static Random Access Memory Using a Resistivity Change Device
1Faculty of Medicine, Graduate School of Medical Science, Kanazawa University, 5-11-80, Kodatsuno, Kanazawa 920-0942, Japan
2Faculty of Engineering, Graduate School of Natural Science & Technology, Kanazawa University, Kakuma, Kanazawa 920-1192, Japan
Received 21 June 2013; Revised 15 October 2013; Accepted 15 October 2013
Academic Editor: Ezz I. El-Masry
Copyright © 2013 Kazuya Nakayama and Akio Kitagawa. This is an open access article distributed under the Creative Commons Attribution License, which permits unrestricted use, distribution, and reproduction in any medium, provided the original work is properly cited.
We proposed and computationally analyzed a multivalued, nonvolatile SRAM using a ReRAM. Two reference resistors and a programmable resistor are connected to the storage nodes of a standard SRAM cell. The proposed 9T3R MNV-SRAM cell can store 2 bits of memory. In the storing operation, the recall operation and the successive decision operation of whether or not write pulse is required can be performed simultaneously. Therefore, the duration of the decision operation and the circuit are not required when using the proposed scheme. In order to realize a stable recall operation, a certain current (or voltage) is applied to the cell before the power supply is turned on. To investigate the process variation tolerance and the accuracy of programmed resistance, we simulated the effect of variations in the width of the transistor of the proposed MNV-SRAM cell, the resistance of the programmable resistor, and the power supply voltage with 180 nm 3.3 V CMOS HSPICE device models.
Power dissipation has been one of the most serious concerns in highly integrated CMOS logic circuits. For example, a leakage current’s effect becomes dominant in the standby mode. One solution is to use nonvolatile memory, which has been proposed. Typical new types of memory include ferroelectric random access memory (FeRAM), magnetoresistive RAM (MRAM), phase change RAM (PRAM), and resistivity change RAM (ReRAM). A nonvolatile SRAM (NV-SRAM) has also been developed to mitigate restriction in program cycles and to improve the access time [1–5]. The component count of the NV-SRAM is large because the nonvolatile portion must be added to the SRAM portion.
The large resistivity change of ReRAM and PRAM is a superior characteristic and has been studied for multivalued nonvolatile memory [6–10]. For example, 16 separate states for multivalued storage were reported in . ReRAM has been widely expected for use as the next generation of nonvolatile memory because of its superior characteristics, such as low-voltage operation, high-speed performance, and low power. This device has two switching modes: unipolar switching, in which the device depends on the pulse width and amplitude of the applied voltage, and bipolar switching, in which the device depends on the polar character. In this paper, we used a bipolar switching device that made the best use of this proposed circuit. Figure 1 shows the definition of the set and reset operations for the bipolar switching device. Set is defined as an operation conducted to change from a high resistance state (HRS) to a low resistance state (LRS), and reset is an operation to change from LRS to HRS.
In this paper, we apply the multivalued storage technology to the NV-SRAM. The proposed multivalued nonvolatile SRAM (MNV-SRAM) can hold 2 bits (4 values) of memory in standby mode and acts as conventional SRAM in a normal (SRAM) operation. By replacing half of the conventional SRAM array with MNV-SRAM cells, NV-SRAM memory is realizable, as shown in Figure 2(a). The number of elements (transistor and resistor) required to hold 1 bit can be reduced using the proposed MNV-SRAM cells. Furthermore, when all of the cells are replaced with MNV-SRAM cells, as shown in Figure 2(b), the capacity becomes twice that of the conventional memory. We also propose a stable recall operation. The recall operation of conventional NV-SRAM with the programmable resistor is not very stable. It will become even more unstable since process variations increase along with the progress of scaling in CMOS technology.
In this paper, we describe the cell’s design and operation. We also present the results from the HSPICE simulation of the proposed MNV-SRAM cell using a 180 nm 3.3 V CMOS device model.
2. Cell Structure and Operation
Figure 3 outlines the circuit topologies of conventional NV-SRAM and the proposed MNV-SRAM. The former 8 transistor 2 resistor (8T2R) cell is an improved cell for the conventional shadow RAM [1, 2] and has been applied to magnetic tunnel junctions (MTJs) . The latter 9 transistor 3 resistor (9T3R) cell, which is added to the former 1 resistor () and 1 transistor (M9), also consists of standard SRAM portions and the nonvolatile memory portion. , , and are fixed reference resistors and is a programmable resistor. These reference resistors and the programmable resistor are connected to the storage node (S1 and S2) of a standard SRAM cell.
The proposed MNV-SRAM cell has two reference resistors ( and ). By having two reference resistors, the reference resistance can be changed to three values, , , and the parallel resistance of and () as shown in Figure 4. For example, the reference resistance can be changed into 100 kΩ, 65 kΩ, and 39 kΩ, when and are set to 100 kΩ and 65 kΩ, respectively. Therefore, 4 values (2 bits) can be determined as shown in Figure 4(b). It is not necessary to prepare three reference resistances (, , and ). The resistance of depends on material (composition), size, and write/erase pulse conditions. It is necessary to define and according to the resistance distribution of . For simplicity, in this paper, it is assumed that the distribution of is uniform from 0 to 150 kΩ and and are assumed to be fixed resistors which used high resistance polysilicon, and so forth.
The operation scheme, associated with control signals, and main current flows for the proposed MNV-SRAM are outlined in Figure 5. In order to read 2-bit information, the read operation is performed twice in the recall operation. The SRAM + MNV-SRAM array (Figure 2(a)) is used for introduction to the recall operation, and is smaller than . The store operation is also introduced in this paper.
2.1. Recall Operation
It is assumed that stores (holds) 4 values (2 bits) in this paper. In the first recall operation, CLm, CLa, and CLb are set to “H,” “L,” and “H,” respectively (M7 and M9 are turned on and M8 is turned off). Therefore, can be compared to (Figure 4(a2)). During recall, transistors M7 and M9 are turned on. A certain current (or voltage) is applied from the precharge circuit (i) before/Cpm is set to the “L” state. The voltage of nodes S1 ((S1)) and S2 ((S2)) in Figure 5(a) increases depending on and . When is larger than , (S1) is lower than (S2). Therefore, the information stored in can be recalled into the SRAM portion of MNV-SRAM after/Cpm is set to the “L” state (when the power supply for the cell is turned on). Then, the recalled data is moved from MNV-SRAM to SRAM using read and write circuits. The high-order bit is read out in this process.
In the second recall operation, both CLm and CLa are set to “H.” CLb depends on the results of the first recall operation. When is smaller than , CLb is set to “H.” is compared to (Figure 4(a3)). On the other hand, when is larger than , CLb is set to “L.” is compared to (Figure 4(a1)). The low-order bit is read out in this process.
This recall step and read-out of 2-bit data are shown in Figure 6.
2.2. SRAM Operation
Normal SRAM operations can be performed by closing transistors M7, M8, and M9, as shown in Figure 5(b).
2.3. Store Operation
Figures 5(c) and 5(d) outline the store operation, which is performed just before power off. The information stored in SRAM (high-order bit) and (SRAM part of) MNV-SRAM (low-order bit) in Figure 5(a) is read first. The reference resistor is selected by this read information. For example, when the read information is “01,” needs to be set between and . When is larger than , the set pulse needs to be applied to . When is smaller than , the reset pulse needs to be applied to as shown in Figure 7.
In order to compare with , CLm, CLa, and CLb are set to “H,” “L,” and “H,” respectively. Then, the recall operation is carried out. When is larger than , node S2 is automatically set to “L” (0 V) in this recall operation. A set voltage (required for set operation) is applied from PL. After that, the set pulse is applied to in order to make have a lower resistance, as shown in Figure 5(c). On the other hand, when is smaller than , the V(S2) is set to “H” automatically. The current which flows through is zero (or a small value) because the voltage of both ends of is high (H).
Next, all of CLm, CLa, and CLb are set to “H” and the recall operation is carried out. is compared to . When is smaller than , node S2 is set to “H” automatically in this recall operation. Then, the PL is set to low voltage (or 0 V). The reset pulse is applied to , as shown in Figure 5(d). On the other hand, when is larger than , node S2 is set to “L” automatically. The current that flows through is zero (or a small value) because the voltage of both ends of is low.
Table 1 shows the relationship of , the nodes potential (S2 and PL), and the applied pulse.
3.1. Simulation Condition
The device characteristics of the ReRAM are assumed in Table 2 . These data are the set/reset conditions for a single-level cell using CoOx . The resistance of the set state was 5 kΩ and the resistance of the reset state was reported to be within 10 kΩ and 150 kΩ. Then, it was assumed that changes from 10 kΩ to 150 kΩ, and the set and reset voltages were assumed to be lower than the values shown in Table 2. 1024 cells were connected in a bit line (BL), as shown in Figure 2. Here, peripheral control circuits, such as address decoding and timing generation, are not included in our simulation condition. The wiring capacity and the wiring resistor are not included, either. The simulation conditions are listed in Table 3.
3.2. Recall Operation
Figures 8 and 9 show the simulation results for the recall operation. and were fixed at 100 kΩ and 65 kΩ, respectively. In this case, the reference resistances , , and are 100 kΩ, 65 kΩ, and 39 kΩ, respectively.
First, /Cpm was set to “H” and nodes S1 and S2 were charged once by 0 V. Voltage (current) was applied to the BL, /BL, and PL using the precharge circuit (i) and (ii). A recall pulse of 600 mV was produced from the precharge circuit (i) (at 41 ns). When was 50 kΩ, the voltage nodes S1 and S2 at 65 ns were 350 mV and 570 mV, respectively. The difference voltage () at 65 ns) was −220 mV. Since the voltage of node S1 was lower than that of node S2, after /Cpm was set to “L” (at 66 ns), nodes S1 and S2 could be set to “L” and “H,” respectively. Next, this recalled data was moved from MNV-SRAM to SRAM using read and write circuits.
Second, /Cpm was set to “H” and nodes S1 and S2 were again charged by 0 V. The recall pulse of 600 mV was applied to the BL and /BL using the precharge circuit at 220 ns. When was 50 kΩ, the voltage nodes S1 and S2 at 229 ns were 550 mV and 460 mV, respectively. The difference voltage ( at 229 ns) was 90 mV. Since the voltage of node S1 was higher than that of node S2, after /Cpm was set to “L” (at 230 ns), nodes S1 and S2 could be set to “H” and “L,” respectively. Therefore, when is 50 kΩ, the information “01” is recalled in this way.
3.3. Store Operation
When the information “01” is stored in , needs to be set between 65 kΩ () and 39 kΩ (=). There are three cases for the store operation, as shown in Figure 7. Figure 10 shows the simulation results for this store operation. It was confirmed that the circuits operated when the value of was from 10 kΩ to 150 kΩ. When was 150 or 10 kΩ, the set or reset pulse was applied to , respectively. On the other hand, when was 50 kΩ, the electric pulse did not need to be applied to . The recall operation and the decision operation of whether or not the write pulse is required could be performed simultaneously. Therefore, the decision operation and circuit are not required when using this proposed scheme.
4.1. Number of Elements of the Proposed Cell
Conventional MNV-SRAM cells consist of 8T2R, as shown in Figure 3(a) [1, 2, 4]. The proposed MNV-SRAM cell can hold 2 bits (4 values) of memory in standby mode by adding 3T3R to a SRAM (6T) cell. In the array structure shown in Figure 1(a), 2 bits are recorded in 2 cells (SRAM + MNVSRAM, 6T + 9T3R). Therefore, the average number of elements required in order to memorize 1 bit of memory (ANE) is 7.5T1.5T, using the proposed MNV-SRAM cell. By using the proposed cell, the number of elements per cell can be reduced by 0.5T0.5R.
If the number of reference resistors is increased, a cell can memorize much more information theoretically. For example, the cell with three reference resistors can encode 3 bits/cell, and the cell with four reference resistors can memorize 4 bits/cell. Therefore, ANE decreases with an increase in the quantity memorized per cell, as shown in Table 4. However, a read/write margin rapidly decreases with an increase in the quantity memorized per cell.
4.2. Recall Stability
One of the most serious problems with MNV-SRAM is the stability of recall. The data integrity of the proposed MNV-SRAM cell is dominated by recall since all resistance information must be properly regenerated to the corresponding SRAM and SRAM portion of MNV-SRAM. The recall operation is used also for the store operation. The effect of variations in device characteristics (device mismatch) on recall is described below. Figure 11 plots the effect of the channel width of the transistor on recall. For simplicity, we have only shown that the width of the channel of NMOS transistor M2 in Figure 3(b) varied by 20%. , , and were fixed at 100, 65 and, 50 kΩ, respectively. For example, when the width is narrowed by −20%, the decreases (−220 mV (0%) −174 mV (−20%)) at 65 ns. However, the increases slightly (90 mV (0%) 115 mV (−20%)) at 229 ns. In all cases, the recall operation was performed correctly. However, the precharge operation is not used in the conventional recall operation . The recall operation easily malfunctions without the precharge operation. For example, if the width of NMOS transistor M2 is narrowed by 1%, the recall operation malfunctions without the precharge process.
Figure 12 shows the effects of power supply voltage fluctuations. The supply voltage varied from −30% to 0%. The recall operation was correctly executed for the supply voltage fluctuations. However, a drop in the supply voltage to −30% reduced the voltage difference to 30 mV (−220 mV −190 mV at 65 ns).
Figure 13 shows the effect of fluctuations. showed different voltages between the nodes S1 and S2 (). was compared to , and was fixed at 65 kΩ. varied from 40 to 90 kΩ. The threshold resistance was 67 kΩ and it was a little bigger than . It seems that the threshold resistance shifted, since the number of resistors (FETs) connected to S1 ( and ) and S2 () differed. The recall operation is easy when the absolute value of is large. If the absolute value of must be 100 mV or more, must be smaller than 65 kΩ or larger than 70 kΩ in this study. If the circuits are optimized, these points could improve.
4.3. Reference Resistor
In order to enlarge a read margin, it is necessary to enlarge the reference resistance differences. Figure 14 shows the reference resistances and the differences between the reference resistances. was fixed at 100 and was changed from 0 to 100. The differences of the reference resistances reached a maximum by = 2. For example, the values of and were set to 100 kΩ and 71 kΩ, respectively. Then, the value of was set to 42 kΩ.
4.4. Energy Break Even Time
The energy break even time (EBT)  is also important for MNV-SRAM. The EBT depends on write/recall energy, the leakage current of FETs, and so forth. However, it is difficult to estimate the EBT because the energy-consuming write/verify cycles are usually required in multivalued nonvolatile memory. Therefore, the EBT also depends on the number of write/verify cycles. Although it was a rough estimate, we estimated the EBT by the following easy model. The set/reset condition in  (Table 2) and its behavior model  were used. The write energy was assumed to be the average of set and reset energy as reported by Kawabata et al. . Write and recall cycles were only one cycle each and the verifying cycle was zero. It was estimated that the EBT was 0.5 s in this condition. The EBT would improve when low power operating devices (materials) were used and/or the circuits were optimized.
We proposed a MNV-SRAM using a ReRAM. The proposed 9T3R MNV-SRAM cell can store 2 bits of memory and achieve stable recall against process variations and extended program cycles.
In order to realize the stable recall operation, a certain current (or voltage) is applied to the cell before the power supply is turned on. The voltage of nodes S1 and S2 of cells increases depending on and . When is larger than , (S1) is lower than (S2). Therefore, the information stored in can be stably recalled when the power supply for the cell is turned on.
To investigate the stability of recall, we simulated the effect of variations in the width of the transistor of the proposed NV-SRAM cell, the resistance of the sample, and the power supply voltage. For example, when the channel width of the transistor of the cell is narrowed by −20%, the decreases (from −224 mV (0%) to −174 mV (−20%)) at 65 ns. On the other hand, the increases slightly (from 92 mV (0%) to 115 mV (−20%)) at 229 ns. Be that as it may, the recall operation was performed correctly.
In the store operation, the recall operation and the decision operation of whether or not the write pulse is required can be performed simultaneously. The decision operation and circuit are not required when using this proposed scheme.
This work was supported by VLSI Design and Educational Center (VDEC), The University of Tokyo, in collaboration with Cadence Design Systems, Inc., Synopsys, Inc., and Mentor Graphics, Inc. The VLSI chip in this study has been fabricated in the chip fabrication program of VDEC, the University of Tokyo, in collaboration with Rohm Corporation and Toppan Printing Corporation. This work was also supported by a Grant-in-Aid for Scientific Research (C) (23560391).
- S. Eaton, D. Butler, M. Parris, D. Wilson, and H. Mcnellie, “A ferroelectric nonvolatile memory,” in Proceedings of the International Solid-State Circuits Conference(ISSCC '88), pp. 130–131, 1988.
- S. Masui, T. Ninomiya, T. Ohkawa et al., “Design and application of ferroelectric memory based nonvolatile SRAM,” IEICE Transactions on Electronics, vol. E87-C, no. 11, pp. 1769–1776, 2004.
- M. Takata, K. Nakayama, T. Izumi, T. Shinmura, J. Akita, and A. Kitagawa, “Nonvolatile SRAM based on phase change,” in Proceedings of the 21st IEEE Non-Volatile Semiconductor Memory Workshop (NVSMW '06), pp. 95–96, February 2006.
- S. Yamamoto and S. Sugahara, “Nonvolatile static random access memory using magnetic tunnel junctions with current-induced magnetization switching architecture,” Japanese Journal of Applied Physics, vol. 48, no. 4, Article ID 043001, 2009.
- A. Kitagawa and K. Nakayama, “Phase change nonvolatile SRAM and Resister',” in Proceedings of the 21th Symposium on Phase Change Optical information Storage (PCOS '09), pp. 33–36, 2009.
- J. Maimon, E. Spall, R. Quinn, and S. Schnur, “Chalcogenide-based non-volatile memory technology,” in Proceedings of the IEEE Aerospace Conference, vol. 5, pp. 2289–2294, March 2001.
- K. Nakayama, M. Takata, T. Kasai, A. Kitagawa, and J. Akita, “Pulse number control of electrical resistance for multi-level storage based on phase change,” Journal of Physics D, vol. 40, no. 17, article 009, pp. 5061–5065, 2007.
- Y. Yin, K. Ota, T. Noguchi, H. Ohno, H. Sone, and S. Hosaka, “Multilevel storage in N-doped Sb2Te3-based lateral phase change memory with an additional top TiN layer,” Japanese Journal of Applied Physics, vol. 48, no. 4, Article ID 04C063, 2009.
- S. Lee, J.-H. Jeong, T. S. Lee, W. M. Kim, and B.-K. Cheong, “Bias polarity dependence of a phase change memory with a Ge-doped SbTe: a method for multilevel programing,” Applied Physics Letters, vol. 92, no. 24, Article ID 243507, 2008.
- Y. Han, K. Cho, and S. Kim, “Characteristics of multilevel bipolar resistive switching in Au/ZnO/ITO devices on glass,” Microelectronic Engineering, vol. 88, no. 8, pp. 2608–2610, 2011.
- S. Kawabata, M. Nakura, S. Yamazaki et al., “CoOx-RRAM memory cell technology using recess structure for 128Kbits memory array,” in Proceedings of the IEEE International Memory Workshop (IMW '10), pp. 16–19, May 2010.
- K. Usami and N. Ohkubo, “A design approach for fine-grained run-time power gating using locally extracted sleep signals,” in Proceedings of the 24th International Conference on Computer Design (ICCD '06), pp. 155–161, October 2006.
- T. Handa, Y. Yoshimoto, K. Nakayama, and A. Kitagawa, “Novel power reduction technique for ReRAM with automatic avoidance circuit for wasteful overwrite,” Active and Passive Electronic Components, vol. 2012, Article ID 181395, 11 pages, 2012.