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International Journal of Antennas and Propagation
Volume 2012 (2012), Article ID 234263, 19 pages
Digital Architectures for UWB Beamforming Using 2D IIR Spatio-Temporal Frequency-Planar Filters
1Electrical and Computer Engineering, The University of Akron, Akron, OH 44325-3904, USA
2Electrical and Computer Engineering, The University of Calgary, Calgary, AB, T2N 1N4, Canada
Received 14 May 2012; Accepted 19 June 2012
Academic Editor: Marco Antonio Panduro-Mendoza
Copyright © 2012 Soumya Kondapalli et al. This is an open access article distributed under the Creative Commons Attribution License, which permits unrestricted use, distribution, and reproduction in any medium, provided the original work is properly cited.
A design method and an FPGA-based prototype implementation of massively parallel systolic-array VLSI architectures for 2nd-order and 3rd-order frequency-planar beam plane-wave filters are proposed. Frequency-planar beamforming enables highly-directional UWB RF beams at low computational complexity compared to digital phased-array feed techniques. The array factors of the proposed realizations are simulated and both high-directional selectivity and UWB performance are demonstrated. The proposed architectures operate using 2's complement finite precision digital arithmetic. The real-time throughput is maximized using look-ahead optimization applied locally to each processor in the proposed massively-parallel realization of the filter. From sensitivity theory, it is shown that 15 and 19-bit precision for filter coefficients results in better than 3% error for 2nd- and 3rd-order beam filters. Folding together with Ktimes multiplexing is applied to the proposed beam architectures such that throughput can be traded for K-fold lower complexity for realizing the 2-D fan filter banks. Prototype FPGA circuit implementations of these filters are proposed using a Virtex 6 xc6vsx475t-2ff1759 device. The FPGA-prototyped architectures are evaluated using area (A), critical path delay (T), and metrics AT and AT 2. The L2 error energy is used as a metric for evaluating fixed-point noise levels and the accuracy of the finite precision digital arithmetic circuits.
Radio-frequency (RF) two-dimensional (2D) infinite impulse response (IIR) space-time (ST) plane-wave frequency-planar beam filters  have potential applications in ultra-wideband (UWB) directional filtering of propagating electromagnetic far-field plane-waves. Such plane-wave filters achieve highly directional beamforming for aperture array applications. The proposed beam filters are designed using the concept of frequency-planar resonant 2D inductor-capacitor (LC) ladder network prototypes having resistive terminations . For example, UWB beam filters can be employed in radar , wireless communications , radio astronomy , and electromagnetic imaging, and sensing . Furthermore, new applications have been proposed in cognitive radio towards enhanced access to radio spectrum (EARS)  which requires sensitive spectrum sensing in both space and time domains , in turn leading to a strong need for low-complexity directional filters capable of real-time RF operation .
High attenuation in the stop-band region as well as a sharp transition from filter passband to stop-band is greatly desired in high-performance beamforming systems because such characteristics are important for achieving a better approximation to the ideally “brick-wall” type transition between main beam and stop-band null of the array pattern. The sharpness of the transition from passband (main beam) to stop-band (null region) of the aperture array factor directly depends on the order of the transfer function of the spatio-temporal filter that is employed for UWB beamforming. The primary objective of this work is to explore the real-time hardware architectures that are necessary for realizing frequency-planar beam plane-wave filters corresponding to 2nd- and 3rd-order 2D passive LC ladder low-pass networks. The proposed architectures are an extension of the elementary 1st-order hardware architecture described in . Here, we propose novel massively parallel digital architectures with detailed design equations and complexity studies for beamforming networks based on LC-ladder prototypes of order 2 and 3 having significantly better UWB directionality compared to available 1st-order realizations .
The 2D frequency-planar beam filters are both practical bounded-input and bounded-output (practical-BIBO) stable  and structurally stable under zero initial conditions (ZICs) and can be designed for low computational complexity. We propose massively parallel systolic-array VLSI architectures containing identical and locally interconnected parallel processing core modules (PPCMs) for 2nd-order and 3rd-order beam filters. The proposed architectures are fine-grain pipelined using both inter-PPCM and intra-PPCM registers in order to reduce the critical path delays (CPDs) for achieving maximum clock frequency and temporal bandwidth. The main reason to pipeline the filters is to achieve higher throughputs required for real-time filtering of 2D RF signals derived from time synchronously sampled UWB uniform linear arrays (ULAs) of antenna elements. The proposed systolic-array architectures achieve real-time RF plane-wave filtering at a throughput of one-frame-per-clock-cycle (OFPCC). The frame sampling rate of the beamformer is equal to the clock frequency Hz.
An approximately frequency-independent beam shape over an UWB frequency range is obtained by employing a fan filter bank configuration where each subband of the fan filter bank consists of a temporally bandpass frequency-planar beam filter . For the best real-time throughput, each subband of the fan filter bank  may be realized using dedicated massively parallel systolic-array processors. However, this technique results in high circuit complexity due to the high degree of parallelism. In this work, we trade throughput for lower circuit complexity by employing a folded architecture for the realization of the fan filter bank. The hardware design approach of folding leads to the time interleaving of multiple 2D filters. Time multiplexing of filter coefficients in folded hardware allows different filters  to share arithmetic hardware thereby reducing the number of multipliers and adders. -times folding results in -fold utilization of hardware at the cost of a -fold loss in ULA linear frame-rate .
2. Review: Beam Filter Design
2.1. Review of UWB Beamforming
Beamforming enables array factors (AFs)  with steerable directional sensitivities which are used to enhance/reject plane-wave signals [16–22]. Real-time UWB beamforming benefits both engineering and scientific applications such as radar [23–26], navigation , wireless communications [18, 28–31], cognitive radio [32, 33], frequency-agile antennas , radio astronomy and RF space imaging [35–45], microwave imaging and remote sensing applications [46–48]. Radio telescopes [49–52] such as the square kilometer array (SKA) [53–55] requires algorithms for real-time UWB beamforming (70 MHz–1.4 GHz) with multiple beams .
Aperture arrays [16–22, 42, 57–65] enable directional enhancement of plane-wave signals  (such as signals from deep space, wireless base stations, etc.). The electronically steerable nature of the beam direction and size makes beamforming an essential signal processing task in many applications including radio astronomy [35–45, 49–52, 66–88], radar and navigation [23–27], and broadband wireless communication systems [18, 29–31]. Algorithms for beamforming require low-noise amplification [69–71] of the analog signals from the aperture arrays.
In digital beamforming, an array of time synchronous A/D converters  leads to the discrete-time signals. Such algorithms are based on either time domain delay-and-sum (DAS) or frequency domain phased array feed (PAF) techniques [16, 19, 73]. In delay-and-sum-based systems, element signals are delayed and added coherently to form a beam. True time delays for each antenna are found for a particular beam direction and inter antenna spacing and are realized as tapped delay lines [74, 75]. In finite impulse response (FIR) beamforming [60, 61, 76, 77], the time delays are implemented as FIR digital filters. This method has high computational intensity compared to the proposed IIR technique. In frequency domain PAF beamforming [57, 58, 65], the digitized DAA signals are converted to frequency domain by evaluating the temporal fast Fourier transform (FFT) [78, 79]. The FFT bins are subsequently multiplied by a complex weight and coherently summed to achieve frequency domain beamforming.
2.2. Principle of 2D IIR Beamforming
Figure 1 shows the overview of the proposed UWB digital beamforming system. The digital input signals of the proposed massively parallel systolic-array architectures are obtained by amplifying and low-pass filtering the continuous-time (i.e., analog) signals from UWB low-noise antennas. Typical choices for the RF sensing antenna are Vivaldi or BAVA antennas; however, other types of broadband antennas such as biconical antennas may also be employed.
UWB beamforming is implemented here using an array of antennas placed at uniform distance along -axis. The principle of UWB beam filtering [2, 80] is to enhance the spectrum of spatio-temporal plane wave propagating with a desired direction of arrival (DOA) of while simultaneously attenuating all undesired signals with spectrum which lie outside the passband of the filters.
From Nyquist sampling theorem, , where is the temporal sampling period and ms−1 is the speed of light in air . The plane-wave signal of interest is denoted by while interference signals are denoted by , respectively. The 2D sampled input signal is of the form where , and corresponding to the number of elements in the ULA. Additive white Gaussian noise (AWGN) in the 2D signal is represented by . The spatial DOA  is measured from the broadside direction of the ULA and is denoted by where and is the corresponding space-time DOA, ,
2.3. Review of 2D Plane-Wave Beam Filters
The 2D IIR plane-wave beam filters can be synthesized  using 2D LC network prototypes. The Laplace transfer function derived from the network is found and subsequently converted to the 2D -domain using the complex map of bilinear transformation. The resulting -domain transfer function leads to a computable 2D difference equation of the filter enabling real-time digital VLSI realization using RF rate systolic-array processors. Examples of a 1st-order beam filter were previously investigated in . An example of 1st-order 3D IIR cone filter-bank was first proposed in .
We here propose a 2nd-order plane-wave filter hardware having useful applications as a building block for achieving fan filter banks. A sharper transition required for aperture arrays can be obtained with higher order filters. Further, we propose 3rd-order plane-wave filter hardware and estimate both complexity, quantization noise level, and performance. The sharper transition (roll-off) for 3rd-order filter in comparison to the 2nd-order filter is demonstrated.
Let the 1D input-output Laplace transfer function of a classical resistively-terminated th-order LC ladder low-pass network shown in Figure 2 be given by The above equation can be converted to a 2D Laplace equation by applying frequency-planar transformation, to (3) to obtain : is mapped to the 2D -domain by applying bilinear transformation to get Note that the above design equations are limited to filter passbands that exist in the second and fourth quadrants of the 2D frequency space. Given that filter stability requires all components to be nonnegative , for beamforming in quadrants one and three (i.e., ), we use nonnegative values in each branch impedance and shunt admittance of the prototype while mirroring the input array signal spatially because such that the passband spectra now fall within quadrants two and four of the frequency space .
To obtain 2D difference equations, we apply the inverse -transform to the above function under ZICs, leading to th-order plane-wave beam filter realizations having general form  For feed-back paths , and . The frequency response of the Laplace domain prototype is obtained by evaluating . The frequency response of the digital realization is obtained in closed form by evaluating . That is, on the 2D unit bicircle . The frequency response may be verified by computing the 2D discrete Fourier transform (DFT) of the unit impulse response and comparing with the closed-form response .
3. Systolic-Array Architecture of 2D IIR Filters
3.1. Difference Equations
In our example design for 2nd-order plane-wave filter shown in Figure 3, we employ parameters , , . For our example of 3rd-order beam filter shown in Figure 4, the design parameters are , , , and the desired is . Table 1 gives the feedback coefficients of the filter for a 1st-order, 2nd-order, and 3rd-order plane-wave beam filters .
3.2. Partially Separable Signal Flow Graphs
In order to reduce digital implementation complexity, we first separate the 2D z-domain transfer function of the beam filters into separable and nonseparable subfilters. These subfilters correspond to spatial, temporal, and spatio-temporal prototype networks. Therefore, the transfer functions are cascaded to form the final 2D filter as shown in Figure 5. Following  to higher-order filters, we propose that the nonseparable function be realized employing a systolic-array consisting of similar parallel processing core modules (PPCMs) which are interconnected to each other such that spatio-temporal feed-forward and feedback paths required for recursive computation of the filter are realized using 2D difference equations.
The input RF waves received by the each antenna in the ULA is passed through LNAs, low pass filtered, samples, and quantized within each ADC. The sampled digital signals are connected to the PPCM input ports. The corresponding outputs are sent through and as shown in Figure 1. The function is implemented as filter with spatial delays and is implemented using temporal delays: Zero-initial conditions (ZICs) of the filter along both discrete space and time dimensions are defined by The temporal ZICs [10, 11] are provided to the design by preloading the input values with zeros. Spatial ZICs are provided by connecting constant value zero as previous state inputs to the first PPCM. The function for an th-order plane-wave beam filter given in (7) is implemented as similar interconnected PPCMs. Realization of for a 2nd-order filter is shown in Figure 6 and for 3rd-order filter as shown in Figure 7.
3.3. Fixed-Point Arithmetic and Quantization Effects
Signed fractional numbers are quantized in a finite precision digital representation, which in this case is based on the two’s complement format. Hence, we quantize the coefficients of 2D digital IIR filters using signed fixed-point arithmetic. The size of registers is designed such that being the size of the input signal where is the total size of the two’s complement number and is the binary point location counted from the rightmost position. Also, we use as the size of the coefficients of the filter. The fixed-point finite register size of multipliers has been designed at . The size of each digital signal representation after each multiplier and adder has been marked at every point in the realization of . The output signal of a given PPCM is provided as one of the inputs to the next PPCM; this requires that the size of the output signal of each PPCM be the same as the size of the input port in the neighbouring PPCM.
3.4. Beam Sensitivity to Filter Coefficient Precision
First-order sensitivity gives a measure of error associated with perturbations in coefficients of the filter. The sensitivity of the 2D beam transfer function of the filter due to changes in the values of the coefficients that results due to quantization is studied next. We consider 1st-order sensitivity function to find the magnitude error of the design . The sensitivity function for 2D beam function is given by Sensitivity helps to find relative error in transfer function with respect to a coefficient. If is a coefficient of the filter, then the relative error in the transfer function of the filter due to perturbations in is given by The gain sensitivity in is computed using The gain sensitivity in due to fixed-point errors in all the coefficients of the filter is given by the summation of the gain sensitivities with respect to each coefficient . We consider nonuniform error in the coefficients given by . The relative error in with respect to different sizes of coefficients for 2nd-order and 3rd-order filters is shown in Figure 8. Relative error  in is calculated as follows: where . From Figure 8 for the usable frequency range , we observe that, for 2nd-order beamformers, -bit precision in the filter coefficients leads to beam accuracy within which improves to better than 0.1% for -bit precision. For 3rd-order beamformers, -bit precision in the filter coefficients leads to accuracy, which improves to better than 0.1% accuracy when the filter coefficient precision is increased to -bits.
3.5. Internal Register/Word Sizes
The word length of the signal at the feedback loop needs to be truncated. To maintain a minimum error, the size of the input signal has been decided based on the maximum value of the output signal. The design has been simulated for various word sizes and compared to the 64-bit precision Matlab outputs. For this experiment, we provided an impulsive UWB signal as an input to the filter because the operation and accuracy of the filter can be tested from the impulse response of the filter.
Tables 2 and 3 show the variation of quantization noise with the word size of the coefficients of the filter and the input size. In general, increased precision in the recursive spatio-temporal feedback sections leads to larger VLSI area and higher power consumption with lower speed due to larger CPDs. A compromise must be found depending on the needs of the target application that balances power, speed, accuracy, and chip area.
3.6. Look-Ahead Speed Optimization
The speed of the designs is maximized using fine-grain pipelining. Multilevel pipelining, that is, both inter-PPCM pipelining and intrapipelining, is used for maximum performance. Intrapipelining refers to internal optimization within the PPCMs. The feedback loop of an IIR filter inside the PPCM can be pipelined using look-ahead pipelining. Inter-PPCM pipelining refers to the pipelining of signal paths outside the PPCMs. The application of look-ahead pipelining to non-separable 2D IIR digital filters was first proposed in . Here, we pipeline each feedback loop of the proposed filters using stable scattered look-ahead pipelining (SLA) [11, 86, 87]. In SLA, additional zeros and poles which are at same angular distance as the original poles are introduced into the transfer function, enabling the CPD of the filter to be reduced.
If the denominator of the transfer function is in the form of , The general equation of -stage SLA pipelining  is given by The feedback loop for 2nd-order beam filter as shown in the following equation is pipelined for 3 stages in our design example: Transfer function for 3-stage look-ahead pipelining of feedback loop is given by where For the 3rd order, the feedback loop is described using the following equation: The transfer function for 3-stage look-ahead pipelining of feedback loop is given by where
Figure 9 shows the realization of of 2nd-order beam filter. is a spatial function. Hence, it is realized as sum of three consecutive 1D outputs given by the PPCMs of . is temporal function and it is realized as consecutive 1D filters as shown in Figure 10. Similar are the realizations for the 3rd-order filter, as shown in Figure 11 and described by Figure 12.
3.7. Time Multiplexing for Folded Architectures
Time-multiplexed systolic-array designs are useful for the design of fan filters  whose transfer function is given in the following. Figure 13 shows how fan filters are designed using time-multiplexed filters and are described using  where are subbands of a perfect reconstruction FIR bandpass filter bank.
Time multiplexing of -filters needs the inputs to be upsampled by with copying [88, 89]. The input signal consists of samples pertaining to each original sample and are passed through the time-multiplexed filter. In Figure 14, we provide an overview of signal flow in time-multiplexed design of the beam filters. These filters give -outputs which are to be demultiplexed before being applied to the fan filter bank perfect reconstruction FIR bandpass filters . The time multiplexing of the folded architecture caused each unit delay to be increased to where is the number of inputs (, in the example provided) and is the clock delay.
The signal flow inside the time-multiplexed PPCM is such that the coefficients of feedback terms of filters are given to a two-input multiplier through a commutating multiplexer. Input signal is given to the other input of multiplier. A counter is used to select feedback coefficient given to multiplexer. We have designed the filter bank with four filters. Hence, the counter runs from 0 to 3 and restarts. Therefore, when there exists filter coefficients, the required counter must continuously count up to . The critical-path delay reduces as the architecture is fine-grain pipelined with SLA pipelining for the feedback path. Figure 15 shows each fully multiplexed multiplier circuit (FMMC) design for beam filters. 2nd-order and 3rd-order time-multiplexed designs are as shown in Figures 16 and 17, respectively, with as in (22).
4. Simulation and Implementation
4.1. The 2D Frequency Response
The obtained 2D magnitude frequency response of a 2nd-order frequency-planar beam plane-wave filter matches the ideal frequency response shown in Figure 18. Figure 19 shows the magnitude frequency response of 3rd-order plane-wave filter. We observe unavoidable warping effect in discrete domain systems due to the use of the 2D bilinear transform. Warping effects can be avoided by temporally oversampling the signal such that the spectrum lies totally within the straight-line region of the beam response. Figure 20 shows contours of the magnitude response of the filters in log scale. Plots for infinite precision, highest fixed-point precision, as well as lowest fixed-point precision are provided. It can be seen that the transition (roll-off) of the 3rd-order plane-wave filter is sharper compared to that of 2nd-order filter. The performance of the designed finite precision digital systolic-array circuit is measured by calculating the error energy due under quantization effects. The output obtained from difference equation (from Matlab, at 64-bit precision) is considered as ideal output, and the error is calculated by the difference of ideal output and the fixed-point measurement from the FPGA device. The energy of the error, , is calculated as follows: where is the Fast Fourier Transform of the ideal output obtained using difference equation from Matlab and is the Fast Fourier Transform of the output obtained from the hardware design. We have tabulated unnormalized -error energies as a metric for quantization noise levels for different values of word sizes for 2nd-order and 3rd-order plane-wave filters in Tables 2 and 3, respectively.
4.2. Broadband Signal Filtering
We demonstrate the directional selectivity of the proposed frequency-planar plane-wave beam filters by employing a Gaussian impulsive ultra-wideband signal  as input to the filter. The input to the filters that is shown in Figure 21(a) is a combination of three signals with space-time DOAs , , and given by where , . We used , , , , such that they have space-time DOA, , , . The 2nd-order beam filter selectively filters signal with space-time DOA of and attenuates the signal (pulse peak) with by 40.11 dB and signal (pulse peak) with by 37.22 dB. Similarly, 3rd-order beam filter selects signal with space-time DOA of and attenuates the signal (pulse peak) with by 50.305 dB and signal (pulse peak) with by 52.2 dB.
The directional attenuation of the signals was calculated using dB where is the magnitude of the attenuated signal. Attenuation in signal energy was calculated by correlation. The directional enhancement of the energy of desired signal (or attenuation of the undesired signal) was calculated using dB. The attenuation in energy of the signal with is 18.78 dB for 2nd-order plane-wave filter and 26.2 dB for 3rd-order plane-wave filter. Energy of the signal with is attenuated by 14.26 dB by 2nd-order plane-wave filter and 26.69 dB by 3rd-order plane-wave filter. We observe that the attenuation of the undesired signals improves for the higher-order plane-wave filter, which confirms that the directional selectivity of a beamformer improves with the order of the filter. Figure 22(a) shows the 2D spectrum of the input Gaussian broadband signal. In Figure 22(b), we show the output of the 2nd-order beam filter, followed by Figure 22(c), which shows the output of 3rd-order beam filter for broadband Gaussian modulated cosine waves.
4.3. Beam Patterns (Array Factor)
Directional enhancement of plane-wave beam filters can be observed through beam patterns of filter at different frequencies. Figure 23 shows comparison between beam patterns of 1st-order filter, 2nd-order filter, and 3rd-order filter for frequencies , , radians, respectively. The polar plot of th-order filter can be obtained using magnitude of the transfer functions which is given by where for feedback loop By substituting , , and in terms of , is made dependent on . The magnitude of normalized function is calculated by The values of for th-order function are same as the values considered for filter design. The plots shown in Figure 23 give the polar plot (in dB scale) of the functions using log scale which means the magnitude of the function is calculated as .
4.4. FPGA-Based ASIC Emulation
We employ FPGA-based logic emulation for low-cost prototyping of potential RF digital application specific integrated circuits (ASICs). The proposed designs of 2nd-order and 3rd-order plane-wave beam filters are implemented on a Xilinx Virtex 6 xc6vsx475t-2ff1759 device for different fixed-point precision levels. The 3rd-order plane-wave beam filter is more complicated compared to 2nd-order filter due to higher multiplier and adder complexity. To ensure place-and-route success, we limit the number of PPCMs to 10 for each case. Implementation was first simulated and then targeted to a Virtex 6 xc6vsx475t-2ff1759 FPGA board. We optimized the real-time clock speed of the proposed designs by applying 3-stage SLA pipelining. These filters were implemented both with and without SLA in order to observe the relative improvement in performance. Tables 4, 5, 6, and 7 show the FPGA hardware resources such as slice registers, look-up tables (LUTs), flip-flops (FFs), CPD, and maximum clock frequency. We observe a reduction in speed of operation of the 3rd-order plane-wave filter due to increased complexity at same level of pipelining as 2nd-order plae-wave filter. Time-multiplexed filters having corresponding folded digital architectures were physically implemented on the same board, and resource consumptions are tabulated in Tables 8 and 9, respectively. Folding and time multiplexing were applied to both designs having the SLA pipelining. At this stage, we use FPGA prototypes for verification of operation at an order of magnitude lower clock frequency than the final expected RF digital realization.
4.5. Computational Complexity
Table 10 shows comparison of computational complexity and throughput for one PPCM between 2nd-order and 3rd-order beam filters for different stages of SLA. VLSI metrics area time (, )  is calculated as a measurement of complexity to find the main constraints in designing the filters. In VLSI systems, is used for cases where low chip area is more important than clock speed. Similarly, is used for cases where clock speed is the driving factor. Table 11 gives measures of both and for 2nd-order pipelined designs, both with and without LA, for different levels of fixed-point precision. Furthermore, Table 12 gives the same metrics for the 3rd-order filter architecture.
Highly directional steerable ultra-wideband digital antenna aperture arrays have useful applications in wireless communications, radar, radio astronomy, spectrum sensing, RF imaging and remote sensing. We propose novel massively-parallel systolic-array architectures for the real-time digital realization of beamforming 2D IIR frequency-planar beam plane-wave filters based on resistively terminated LC ladder networks. The proposed architectures are aimed at 2nd- and 3rd-order beam filters and are based on the recently proposed 1st-order beam filter architecture . These beamformers offer both low computational complexity and UWB performance.
The proposed architectures enable RF throughputs when eventually realized using high-speed CMOS technology. The proposed architectures are evaluated for correct operation, area, time, and complexity metrics as well as beam sensitivity and noise levels as a function of finite precision. Extensive prototype FPGA realizations, simulations, and FPGA-based emulations of beamforming performance are used here to validate the architectures and design procedures for high-performance digital UWB beamforming applications. As part of the proposed optimized designs, a fine-grain pipelined systolic-array 2D IIR plane-wave beam filters of orders 2 and 3 have been designed and optimized using scattered look-ahead to reduce the CPD of the digital circuits. Low CPD results in high real-time throughput with corresponding increase in clock frequency. The architectures were evaluated using CPD (), area (), as well as and .
The proposed 2nd-order design filter architecture is verified using a realistic Gaussian modulated cosine wave input signal consisting of several plane-waves. The filter is designed to enhance the plane-wave having space-time , while attenuating the undesired signal up to 40.11 dB for space-time and 37.22 dB for space-time . Similarly, the 3rd-order filter provided up to 50.305 dB of stopband rejection for space-time and 52.2 dB of stop-band rejection for space-time for a broadband Gaussian-modulated cosine-wave signal. The corresponding hardware architectures were verified on FPGA chip using measured unit impulse responses obtained using stepped FPGA hardware cosimulation. The 2D frequency response of the measured impulse response from the FPGA chip is compared with a reference response obtained from the difference equation by calculating the error energy for different finite precision sizes.
Furthermore, the proposed architectures were folded and time-multiplexed to form a filter bank. The time-multiplexed filters have also been physically implemented on Xilinx Virtex6 xc6vsx475t-2ff1759 FPGA board. Future work involves digital CMOS integrated circuits using ASIC standard cells for RF clock frequencies with applications in UWB real-time electromagnetic beamforming antenna arrays.
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