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International Journal of Photoenergy
Volume 2013 (2013), Article ID 171390, 8 pages
p-Type Quasi-Mono Silicon Solar Cell Fabricated by Ion Implantation
1Institute of Microelectronics & Department of Electrical Engineering, Center for Micro/Nano Science and Technology, Advanced Optoelectronic Technology Center, National Cheng Kung University, Tainan 70101, Taiwan
2Inventec Solar Energy Corporation, Taoyuan 335, Taiwan
Received 2 January 2013; Revised 3 March 2013; Accepted 13 March 2013
Academic Editor: Peter Rupnowski
Copyright © 2013 Chien-Ming Lee et al. This is an open access article distributed under the Creative Commons Attribution License, which permits unrestricted use, distribution, and reproduction in any medium, provided the original work is properly cited.
The p-type quasi-mono wafer is a novel type of silicon material that is processed using a seed directional solidification technique. This material is a promising alternative to traditional high-cost Czochralski (CZ) and float-zone (FZ) material. Here, we evaluate the application of an advanced solar cell process featuring a novel method of ion implantation on p-type quasi-mono silicon wafer. The ion implantation process has simplified the normal industrial process flow by eliminating two process steps: the removal of phosphosilicate glass (PSG) and the junction isolation process that is required after the conventional thermal POCl3 diffusion process. Moreover, the good passivation performance of the ion implantation process improves . Our results show that, after metallization and cofiring, an average cell efficiency of 18.55% can be achieved using 156 × 156 mm p-type quasi-mono silicon wafer. Furthermore, the absolute cell efficiency obtained using this method is 0.47% higher than that for the traditional POCl3 diffusion process.
The photovoltaic (PV) industry has benefited from the policies of many successive governments that have offered incentives for power projects such as rooftop solar systems. The resulting increase in demand has grown the solar energy market by at least 20% per annum over the past ten years. The final target of the PV industry is the achievement of grid parity, and lowering manufacturing costs and increasing efficiency are very important steps in achieving this target. Reducing silicon bulk thickness and substituting alternative cheap materials are just two options available for lowering the initial cost of materials. In particular, reducing silicon bulk thickness will increase the amount of wafer per ingot or brick, thereby reducing the price per watt. However, this could produce a wafer handling issue, resulting in a higher wafer breakage rate during cell and module processing.
Substituting alternative cheap materials is one solution to reduce cost. Multicrystalline silicon (mc-Si) substrates have traditionally been used in industrial solar cells owing to their relatively low cost, particularly compared to that of Czochralski (CZ) grown monocrystalline material. However, they can suffer from low efficiency due to defects attributed to grain boundaries. In this study, we use a p-type quasi-mono wafer as the starting material. Single-crystal silicon is produced according to a seed directional solidification technique  typically used for multicrystalline ingots. The p-type quasi-mono wafer produces higher cell efficiencies than those of multicrystalline silicon material with the same average minority carrier lifetime [1, 2].
Increasing solar cell efficiency will also leverage cost in the solar chain. Solar cell efficiency can be improved by various process methods, including metal-wrap-through (MWT) solar cells [3, 4], emitter-wrap-through (EWT) cells [5, 6], interdigitated backside contact (IBC) cells [7, 8], laser-fired contact cells [9, 10], and ion-implanted cells [11, 12]. Of these methods, ion implantation is one of the most attractive and cost-effective options.
In the present study, we substitute ion implantation for thermal POCl3 diffusion in commercial silicon solar cells, which allows us to eliminate two process steps: (1) phosphosilicate glass (PSG) removal and (2) parasitic junction isolation. In the conventional process, PSG is generated on the surface as a result of the reaction between phosphorous and oxygen during the thermal diffusion step. Accordingly, after thermal POCl3 diffusion, an isolation process is typically required to remove the PSG layer. Moreover, there are two ways to isolate the parasitic junction in the traditional process: wet isolation combined with a PSG clean step and laser isolation. However, both of these isolation processes result in a reduction of the area of the absorption surface; in particular, laser isolation damages the wafer surface and causes lower efficiency.
Here, we used p-type quasi-mono silicon wafers (GCL-Poly Energy Holdings Limited) with resistivities of 0.5–3 Ωcm, thicknesses of 180–200 μm, and dimensions of mm. A monocrystalline seed was placed at the bottom of a crucible, and polysilicon was then loaded on top of the seed. The underlying seed allowed quasi-mono silicon ingots to grow in the DS furnace. We selected 9 ingots from the center of the brick for use as starting material. These 9 ingots had more than 90% of their area oriented in the direction and less than 10% in other directions. We sliced the 9 ingots into wafers. Figure 1 illustrates the distribution of these 9 ingots within the brick. Figure 2 presents a comparison of the process flow for conventional thermal POCl3 diffusion with that for ion implantation on quasi-mono silicon wafers. Because the crystalline area constituted more than 90% of ingot area, an alkaline texturing method was used, and processing was conducted using a Rena alkaline machine. First, a saw damage removal step was required in order to reduce surface stress caused by the wire saw used. Wafers were dipped in a batch type system with Teflon material with a high KOH concentration (5.04 wt%) without IPA solution mixing for the saw damage removal process step. Then, anisotropic etching with a KOH : IPA : H2O volume ratio of 1 : 1.6 : 34 was conducted to produce pyramids on the surface to absorb incoming light and increase the light path in the silicon bulk. In the commercial process, the next step would typically be thermal POCl3 diffusion to form a p-n junction. Here, a diffusion furnace (Tempress Systems, The Netherlands) was used to perform thermal POCl3 diffusion. Also, 400 wafers were placed vertically into a quartz boat; then, the boat was moved into a quartz tube and heated to 840°C. The dopant gas reacted with the silicon surface in the presence of O2 at high temperature, with the following reactions taking place:
In the ion implantation process, an inline high-throughput machine (>1000 pcs/hr) from Varian Semiconductor Equipment Associates (VSEA) was used to perform ion implantation. Ion dopant bombarded the wafer surface, subsequently penetrating into the wafer. We selected PH3 gas as the P+ ion source for implantation on the surface, with a low beam energy of 10 keV and a dose of 3.0 × 1015 P+/cm2. However, crystal damage occurred during the ion bombardment procedure. Inclusion of a high-temperature annealing process step can recover this damage. A furnace tube from Tempress Systems was used for thermal annealing. In the annealing step, wafers were placed vertically into a quartz boat, and the boat was moved into a quartz tube. Dry oxide (O2) was passed into the tube, activating the dopant. Simultaneously, a thinner silicon oxide formed on the wafer surface according to the following reaction:
The dry oxide annealing step was conducted to activate the dopant and fabricate the junction. After annealing, the dopant concentration profile was different from that for POCl3 diffusion [13–16]. According to previous studies, the doping concentration profile of POCl3 typically ranges from an error function complement (erfc) to a Gaussian distribution, with the peak dopant concentration occurring at the surface. Conversely, the profile for ion implantation occurs at a specific depth below the surface. Detailed discussions of these profiles can be found in previous studies [13–16].
After emitter formation, an isolation process was conducted to remove the parasitic junction caused by POCl3 diffusion during the industrial process flow. A chemical isolation process was performed with an inline roller type transportation system using the InOxSide instrument from Rena GmbH. In this process step, the parasitic junction was removed in an etching bath with H2O : HF : HNO3 : H2SO4 volume ratio of 19 : 2 : 11 : 8.
After the isolation/annealing step, layer was applied to act as an antireflection coating (ARC). Wafers were automatically placed into a batch type system machine from Centrotherm, and the layer was applied by direct plasma deposition. The layer not only absorbs more light into silicon, but also passivates the silicon surface. Moreover, the thickness of silicon nitride used in the implantation process in the present study was thinner than that for the conventional POCl3 process owing to the thinner silicon oxide layer formed on the wafer surface during the annealing step in the ion implantation process.
After ARC deposition, a metal contact was formed by a Baccini belt type screen printing system and a Despatch cofiring system. During the screen printing process, frontside silver (Ag) paste, Dupont 17F, was printed on the frontside surface to form three bus bars and 83 finger lines. Dupont PV-157 was used as the backside Ag paste and Monocrystal RX-1203 as the backside aluminum (Al) paste.
Berger Lichttechnik single-pulse solar simulators were used to measure the basic parameters and curves of cells under standard test conditions (STCs): irradiance of 1000 W/m², the AM 1.5 solar spectrum, and temperature of 25°C. Electrical characteristics (including , , FF, , and cell efficiency) were obtained from the curves. The shunt resistance was determined from the linear slope of the reverse dark current for each cell. The series resistance was calculated from two curves measured at 1000 W/m² and 500 W/m², according to IEC 891.
3. Results and Discussion
Here, we textured 2000 samples of p-type quasi-mono silicon simultaneously. Figure 3 shows the appearance of the quasi-mono silicon after texturing, illustrating the many different grains that appear on the surface. Figure 4 illustrates the pyramid topology revealed at different locations within the wafer for 30x (Figure 4(a)) and 550x (Figure 4(b)) SEM at the upper right of the wafer. Three different pyramid orientations are shown. Figures 4(c) and 4(d) also illustrate the pyramid topology for 95x and 350x SEM at the upper right of the wafer, respectively; these are clearly different from Figures 4(a) and 4(b). The figure indicates that quasi-mono silicon wafer exhibits a planar area after alkaline texturing. Figures 4(e) and 4(f) illustrate the pyramid topology for 30x and 550x SEM at the upper left of the wafer and indicate that scrapes have appeared on the quasi-mono silicon wafer. Such differences in topology can be seen clearly after alkaline texturing and are likely due to differences in grain boundaries.
After texturing, a Hitachi U-4100 UV-Vis-NIR spectrophotometer was used to measure the reflection. U-4100 has two light sources that can measure reflection at wavelengths of 240–2600 nm and an integrating sphere that can measure textured wafer. We selected 4 wafers randomly from each group and measured 5 points at 5 different locations within each wafer. Figure 5 illustrates a comparison of the reflection from these different locations after the alkaline texturing process.
As the figure shows, there are small differences in reflections between locations. This is likely due to the different pyramid topologies caused by different grain boundaries. To quantify the performance, we calculated the weighted reflectance % based on a previously published study  as follows: where () is the photon flux and () is the cell internal quantum efficiency [18, 19]. Table 1 presents a comparison of % for 5 different locations within the wafers and indicates that % is highest for the upper right location at 13.92%. This corresponds to an area with a shiny appearance caused by a different pyramid orientation and planar topology. Conversely, the lowest % (12.94%) was found for the center location and is thought to be due to the single-crystalline structure in the center.
After texturing, the next step in the ion implantation process was ion implantation itself. For this, 1600 wafers were automatically transferred into the chamber, and P+ ion sources were implanted onto the wafer surface from the ion source. Then, we divided the 1600 wafers into 4 groups, each with 400 wafers.
These 4 groups were processed at peak temperatures of 810, 840, 870, and 900°C during the subsequent annealing step. A four-point probe was used to measure the sheet resistance (). Table 2 presents a comparison of and uniformity for POCl3 diffusion and the 4 different annealing processes; in particular, the table indicates that decreased when the peak temperature was 810–900°C and the baseline for the POCl3 diffusion process was 64.68 Ω/sq. The uniformity for thermal POCl3 diffusion was 4.80%, which was worse than that for the implantation process. In fact, the uniformity of the implantation process was below 3%, likely owing to the precise control exercised over the dose amount by the emitter in the ion implantation apparatus. The good uniformity and precise control also enabled a repeatable process for fabrication of lightly doped emitter regions [20–22].
In order to obtain the best performance from the annealing step, 5 p-type quasi-mono wafers, implanted with 2.0 × 1015 dopant ions at a beam energy of 10 keV on both faces of the wafer, were used to monitor the implied and carrier lifetime  for each condition. The WCT-120 tool from Sinton Instruments uses a quasi-steady-state photoconductance (QSSPC) method to measure implied and lifetime . Table 3 presents the average implied and lifetime for each condition. The implied for wafers doped by thermal POCl3 diffusion was found to be 0.625 V at 1 sun. However, the implied after high-temperature annealing at 900°C was 0.620 V, the worst among all conditions studied. This was likely because high-temperature annealing can degrade the lifetime and reduce the . When the annealing temperature was decreased to 840°C, the implied reached 0.640 V; this higher implied was likely due to better surface passivation.
In the annealing step, a thinner SiO2 layer was grown on the wafer surface, and the ion-implanted dopant was activated. The thickness of the SiO2 was measured by a SemiLab LE-100PV ellipsometer. A single laser wavelength from a 632.8 nm He-Ne laser incident on the wafer surface was used to measure the refractive index and thickness of the dielectric layer. In this study, the silicon polished wafer with a dose of 3.2 × 1015 implanted and a beam energy of 10 keV on its surface was used as the control wafer. During the annealing process, control wafers were processed simultaneously with the experimental p-type quasi-mono silicon wafers in the same tube. Table 4 shows the resulting SiO2 thickness and uniformity for each condition. The thickness of SiO2 was found to be around 17 nm and was very similar for all the different conditions. Moreover, the uniformity of SiO2 was improved at higher annealing temperatures, and we found good SiO2 thickness uniformity (below 1.3% for each annealing condition).
After the junction formation step, was deposited on the silicon surface by PECVD. In contrast to the industrial process, the thickness of the silicon nitride must be modulated during this process owing to the thinner oxide on the surface. In order to minimize the reflection from the frontside of the cell, a 57 nm layer was deposited on top of the SiO2. We selected 4 wafers for each condition after the ARC process and measured 5 points at different locations within each p-type quasi-mono wafer. Figure 6 illustrates the comparison of average reflection between POCl3 diffusion and the ion implantation process after deposition of the ARC. At short wavelengths, the reflection from samples treated by POCl3 diffusion was lower than that of samples treated by ion implantation. According to the Schuster diagram , the optimum refractive index of the inner n1 and outer n2 layers of the silicon substrate can be calculated as follows for zero reflection: where
As explained previously, based on detailed calculations , better optical performance can be achieved by using a low-high refractive index design, in which the outer layer has a low refractive index and the inner layer has a high refractive index, on the silicon substrate. However, the design of the ARC in our ion implantation process displayed the opposite characteristics; the outer and inner SiO2 layers had refractive indexes of 2.03 and 1.46, respectively. Such high-low design tends to cause higher reflection at short wavelengths. In the long-wavelength range, the reflection following implantation was lower than that following POCl3 diffusion, because the wafer had a planar backside surface owing to the wet chemical isolation process that used HNO3 and HF to remove the backside p-n junction after POCl3 diffusion. Table 5 presents a comparison of % between POCl3 diffusion and ion implantation after deposition. It is clear that % resulting from implantation was 4.64%, which is better than that from the POCl3 process (which was 5.51% after deposition of the ARC).
After ARC deposition, the wafers were subjected to screen printing and cofiring processes. Figure 7 illustrates a comparison of and between POCl3 diffusion and the implantation process for each condition and indicates that higher annealing temperatures resulted in lower and . The for the implantation process with an annealing temperature of 900°C was the lowest of all, likely because high-temperature annealing can degrade carrier lifetime and ; this is in accordance with the results of the WCT-120 measurements. Based on the heavy doping produced by high-temperature annealing, was lowest following high-temperature annealing at 900°C. When the annealing temperature was reduced to 870°C, reached 0.623 V, which was higher than that for the POCl3 diffusion process. However, was still lower than that for POCl3 diffusion owing to the lower of 61.36 Ω/sq. As the annealing temperature reached 840°C, reached its highest value of 0.636 V. As shown in Figure 8, was highest for the implantation process with an annealing temperature of 810°C, likely because the highest sheet resistance (70.02 Ω/sq) would have produced the worst metal contact. Besides the condition of annealing temperature at 810°C, the of the implantation process is lower than that of POCl3 diffusion process. This was likely due to good uniformity caused by precise doping control by the ion implantation instrument. Moreover, higher annealing temperatures can achieve heavy doping and result in good contact with metal. As shown in Figure 9, the higher annealing temperature also caused a lower , because a higher annealing temperature degrades the bulk lifetime, which lowers . The FF of the implantation process was highest for an annealing temperature of 840°C owing to the lower and higher performances. Moreover, the best average efficiency of 18.55% was found for the implantation process with an annealing temperature of 840°C (Figure 10). All electrical characteristics are presented in Table 6. In general, higher efficiency was found to result from higher and . Therefore, our results indicate that quasi-mono silicon wafer produced by ion implantation can improve photovoltaic cell efficiency. Table 7 presents the cell conversion cost per watt for traditional and implant processes for the quasi-mono wafer substrate. It is clear that the cost of the traditional process (0.1664 USD) was much higher than that of the implant process (0.1617 USD).
In this study, we investigated a novel type of silicon material, the quasi-mono wafer, for use in high-efficiency solar cells. We produced this material by ion-implanted emitter formation and were able to raise the absolute cell efficiency of a quasi-mono silicon wafer by 0.47% by following a simplified process flow that eliminates the PSG strip and junction isolation steps. The uniformity from implantation was found to be better than that from the POCl3 diffusion process owing to the precise dopant control exercised by the ion implantation instrument. After activation by an annealing process, the implied from the implantation process with an annealing temperature less than 900°C was found to be better than that from the POCl3 diffusion process; this was likely due to the good surface passivation caused by the implantation and annealing processes. However, owing to the thinner SiO2 formed on the surface by the annealing process, the thickness of the silicon nitride should be modified to minimize %. After metallization, we achieved an average cell efficiency of 18.55%.
This work was supported by the National Science Council under Contract n. NSC 101-2221-E-006-139. This work was also supported in part by the Center for Frontier Materials and Micro/Nano Science and Technology, National Cheng Kung University, Taiwan. This work was also supported in part by the Advanced Optoelectronic Technology Center, National Cheng Kung University, under projects from the Ministry of Education. The authors wish to thank Professor S. J. Chang of National Cheng Kung University and Haw Yen, COO of Inventec Solar Energy Corporation, for their assistance in this study. This work is supported in part by Inventec Solar Energy Corporation.
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