The Coarse-Grained/Fine-Grained Logic Interface in FPGAs with Embedded Floating-Point Arithmetic Units

Table 4

Minimum channel width (number of wires) for different I/O positions for single EB-type FPGA as shown in Figure 5. The percentage shows the deviation from the 1 side result.

Circuits	1 side	2 sides	3 sides	4 sides
bgm	44 (0%)	44 (0%)	30 (−32%)	27 (−39%)
dscg	43 (0%)	44 (2%)	30 (−30%)	33 (−23%)
bfly	44 (0%)	44 (0%)	38 (−14%)	37 (−16%)
ode	43 (0%)	44 (2%)	35 (−19%)	33 (−23%)
mm3	45 (0%)	45 (0%)	29 (−36%)	30 (−33%)
fir4	42 (0%)	44 (5%)	32 (−24%)	29 (−31%)
Average	43.5 (0%)	44.2 (1.6%)	32.3 (−26%)	31.5 (−28%)