Research Article
High-Level Synthesis of In-Circuit Assertions for Verification, Debugging, and Timing Analysis
Table 2
Edge-detection assertion overhead.
| EP2S180 | Original | Assert | Difference |
| Logic used | 12250 | 12273 | +23 | (out of 143520) | (8.54%) | (8.56%) | (+0.02%) |
| Comb. ALUT | 6726 | 6809 | +83 | (out of 143520) | (4.69%) | (4.75%) | (+0.06%) |
| Registers | 9371 | 9417 | +46 | (out of 143520) | (6.53%) | (6.56%) | (+0.03%) |
| Block RAM | 141120 | 141696 | +576 | (9383040 bits) | (1.50%) | (1.51%) | (+0.01%) |
| Block interconnect | 19904 | 19994 | +90 | (out of 536440) | (3.71%) | (3.73%) | (+0.02%) |
| Frequency (MHz) | 77.5 | 79.3 | +1.8 (+2.32%) |
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