International Journal of Reconfigurable Computing

A New High-Performance Digital FM Modulator and Demodulator for Software-Defined Radio and Its FPGA Implementation

PCIU: Hardware Implementations of an Efficient Packet Classification Algorithm with an Incremental Update Capability

Reduced-Precision Redundancy on FPGAs

Selected Papers from the International Workshop on Reconfigurable Communication-Centric Systems on Chips (ReCoSoC' 2010)

AADL Extension to Model Classical FPGA and FPGA Embedded within a SoC

Sustainable Modular Adaptive Redundancy Technique Emphasizing Partial Reconfiguration for Reduced Power Consumption

A High-Speed Dynamic Partial Reconfiguration Controller Using Direct Memory Access Through a Multiport Memory Controller and Overclocking with Active Feedback

Selected Papers from the 17th Reconfigurable Architectures Workshop (RAW2010)

A Self-Checking Hardware Journal for a Fault-Tolerant Processor Architecture

Exploring Online Synthesis for CGRAs with Specialized Operator Sets

A Middleware Approach to Achieving Fault Tolerance of Kahn Process Networks on Networks on Chips

Static Scheduling of Periodic Hardware Tasks with Precedence and Deadline Constraints on Reconfigurable Hardware Devices

FPGA Acceleration of Communication-Bound Streaming Applications: Architecture Modeling and a 3D Image Compositing Case Study

Exploration of Heterogeneous FPGA Architectures

Boosting Parallel Applications Performance on Applying DIM Technique in a Multiprocessing Environment

International Journal of Reconfigurable Computing

Table of Contents

Table of Contents: 2011

A New High-Performance Digital FM Modulator and Demodulator for Software-Defined Radio and Its FPGA Implementation

PCIU: Hardware Implementations of an Efficient Packet Classification Algorithm with an Incremental Update Capability

Reduced-Precision Redundancy on FPGAs

Selected Papers from the International Workshop on Reconfigurable Communication-Centric Systems on Chips (ReCoSoC' 2010)

AADL Extension to Model Classical FPGA and FPGA Embedded within a SoC

Sustainable Modular Adaptive Redundancy Technique Emphasizing Partial Reconfiguration for Reduced Power Consumption

A High-Speed Dynamic Partial Reconfiguration Controller Using Direct Memory Access Through a Multiport Memory Controller and Overclocking with Active Feedback

Selected Papers from the 17th Reconfigurable Architectures Workshop (RAW2010)

A Self-Checking Hardware Journal for a Fault-Tolerant Processor Architecture

Exploring Online Synthesis for CGRAs with Specialized Operator Sets

A Middleware Approach to Achieving Fault Tolerance of Kahn Process Networks on Networks on Chips

Static Scheduling of Periodic Hardware Tasks with Precedence and Deadline Constraints on Reconfigurable Hardware Devices

FPGA Acceleration of Communication-Bound Streaming Applications: Architecture Modeling and a 3D Image Compositing Case Study

Exploration of Heterogeneous FPGA Architectures

Boosting Parallel Applications Performance on Applying DIM Technique in a Multiprocessing Environment