Research Article
High-Level Synthesis of In-Circuit Assertions for Verification, Debugging, and Timing Analysis
Table 6
Looped backprojection timing assertion overhead.
| EP3SE260 | Original | Assert | Difference |
| Logic used | 48285 | 50169 | +1884 | (out of 203520) | (23.72%) | (24.65%) | (+0.93%) |
| Comb. ALUT | 32962 | 33459 | +497 | (out of 203520) | (16.20%) | (16.44%) | (+0.24%) |
| Registers | 44098 | 44657 | +559 | (out of 203520) | (21.67%) | (21.94%) | (+0.27%) |
| Block RAM | 7114752 | 7123968 | 9216 | (15040512 bits) | (47.30%) | (47.37%) | (0.07%) |
| Block interconnect | 101317 | 102621 | +1304 | (out of 694728) | (14.58%) | (14.77%) | (+0.19%) |
| Frequency (MHz) | 131.9 | 131.3 | −0.6 (−0.45%) |
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