Prime Field ECDSA Signature Processing for Reconfigurable Embedded Systems

Table 6

Performance comparison for signature verification and generation for ECDSA on GF(𝑝). Values marked with an asterisk (*) are only for the core operations scalar multiplication and multiple scalar multiplication, respectively, without all pre- and postprocessing and hashing.

	Bit length |𝑝|	Hardware resources	Clk (MHz)	Generation (kG)		Verification (Kg + rQ)
				Time	#/s	Time	#/s
Microcontroller implementations
Drutarovsky and Varchola [7]	233	ARM7	25	742 ms	1.35	1240 ms	0.8
RIM [9]	256	ARM9EJ-S	N.a.	168 ms	5.95	150 ms	6.7
PC processor implementations
eBACS [6]	256	Motorola PowerPC G4 7410	533	11.7 ms	85.2	14.1 ms	70.7
Petit [37]	256	Intel Pentium D	3400	3.33 ms	300	6.63 ms	151
eBACS [6]	256	Intel Atom 330	1600	2.9 ms	345	3.4 ms	294
eBACS [6]	256	Intel Core 2 Duo U9400	1400	1.88 ms	532	2.2 ms	455
Brown et al. [38]	256	Intel Pentium II	400	*1.67 ms	*599	*6.4 ms	*156
FPGA implementations
McIvor et al. [11]	256	Xilinx Virtex II Pro, 15755 CLB, 256 MUL	39.5	*3.86 ms	*259	N.a.	N.a.
Orlando and Paar [12]	192	Xilinx Virtex-E, 11416 LUT, 35 BRAM	40	*3 ms	*333	N.a.	N.a.
This paper	256	Xilinx Virtex 5, 14256 LUT/FF pairs	20	7.15 ms	140	9.09 ms	110
ASIC implementations
Sakiyama et al. [16]	256	243K gates (0.25 μm)	159	*4.3 ms	*233	N.a.	N.a.
Satoh and Takano [15]	256	120K gates (0.13 μm)	138	*2.68 ms	*373	N.a.	N.a.