Reduced-Precision Redundancy on FPGAs

<table>(a) The pmf of the estimation error, <svg height="11.9625" id="M181" style="vertical-align:-3.3907pt" version="1.1" viewbox="0 0 12.875 11.9625" width="12.875" xmlns="http://www.w3.org/2000/svg" xmlns:xlink="http://www.w3.org/1999/xlink">
<g transform="matrix(.017,-0,0,-.017,.062,7.675)"><path d="M401 397q0 -24 -24 -40q-18 -13 -31 3q-36 45 -93 45q-48 0 -86.5 -43t-51.5 -112l206 6l-8 -48l-203 6v-25q0 -68 26.5 -107t73.5 -39q73 0 148 64l16 -22q-40 -44 -91 -70.5t-102 -26.5q-75 0 -116.5 45t-41.5 136q0 125 99 208q36 30 87 50.5t93 20.5q46 0 72.5 -16
t26.5 -35z" id="x1D716"></path></g>
<g transform="matrix(.012,-0,0,-.012,7.275,11.762)"><path d="M391 364q0 -28 -20.5 -53.5t-50 -43.5t-70 -34t-73.5 -25t-68 -17v-29q0 -48 20 -81t65 -33q73 0 157 76l16 -23q-107 -113 -221 -113q-21 0 -40.5 6.5t-39 22t-31.5 47t-12 75.5q0 69 33.5 139.5t95.5 114.5q77 55 143 55q42 0 69 -24.5t27 -59.5zM313 350
q0 26 -14.5 40.5t-37.5 14.5q-32 0 -44 -7q-82 -46 -104 -175q200 49 200 127z" id="x1D452"></path></g>
</svg>, of an RPR module, (b) the pmf for the maximum undetected upset error signal, <svg height="11.9625" id="M182" style="vertical-align:-3.3907pt" version="1.1" viewbox="0 0 14.3625 11.9625" width="14.3625" xmlns="http://www.w3.org/2000/svg" xmlns:xlink="http://www.w3.org/1999/xlink">
<g transform="matrix(.017,-0,0,-.017,.062,7.675)"><path d="M401 397q0 -24 -24 -40q-18 -13 -31 3q-36 45 -93 45q-48 0 -86.5 -43t-51.5 -112l206 6l-8 -48l-203 6v-25q0 -68 26.5 -107t73.5 -39q73 0 148 64l16 -22q-40 -44 -91 -70.5t-102 -26.5q-75 0 -116.5 45t-41.5 136q0 125 99 208q36 30 87 50.5t93 20.5q46 0 72.5 -16
t26.5 -35z" id="x1D716"></path></g>
<g transform="matrix(.012,-0,0,-.012,7.275,11.762)"><path d="M515 96q-37 -44 -84.5 -76t-71.5 -32q-12 0 -18 7t-6 34t10 75l19 89h-2q-87 -113 -181 -176q-43 -29 -83 -29q-46 0 -46 63q0 31 9 67l52 222q7 36 -1 36q-10 0 -76 -50l-13 24q47 45 92 71.5t67 26.5q18 0 21 -16.5t-8 -65.5l-56 -242q-16 -67 13 -67q41 0 114 74
t114 146l32 145l74 26h11q-52 -199 -80 -347q-8 -39 6 -39q7 0 32 17.5t47 39.5z" id="x1D462"></path></g>
</svg>, and the pmf for (c) a midrange upset which crosses the reduced threshold, <svg height="17.9625" id="M183" style="vertical-align:-3.3907pt" version="1.1" viewbox="0 0 19.049999 17.9625" width="19.049999" xmlns="http://www.w3.org/2000/svg" xmlns:xlink="http://www.w3.org/1999/xlink">
<g transform="matrix(.017,-0,0,-.017,.062,13.688)"><path d="M649 676l-22 -187l-33 -2q3 56 -12 94q-8 20 -31.5 26.5t-86.5 6.5h-74l-90 -491q-4 -23 -6 -36.5t1 -25t7 -16.5t18 -9t27 -5t41 -3l-6 -28h-286l4 28q68 5 84 18.5t28 76.5l94 491h-55q-74 0 -100.5 -6t-41.5 -23q-24 -29 -54 -98l-32 1q32 98 53 188h22q7 -18 15 -22
t37 -4h417q23 0 33.5 5t25.5 21h23z" id="x1D447"></path></g>
<g transform="matrix(.012,-0,0,-.012,11.388,5.525)"><path d="M471 153q-22 -15 -61 -13q-25 31 -45.5 49.5t-56.5 41.5q4 -71 28 -134q-17 -33 -42 -46q-24 12 -42 46q24 63 28 134q-36 -23 -56.5 -41.5t-45.5 -49.5q-36 -2 -61 13q0 28 19 59q65 10 130 43q-65 33 -130 43q-19 31 -19 59q22 15 61 13q25 -31 45.5 -49.5t56.5 -41.5
q-4 71 -28 134q17 33 42 46q24 -12 42 -46q-24 -63 -28 -134q36 23 56.5 41.5t45.5 49.5q36 2 61 -13q0 -28 -19 -59q-65 -10 -130 -43q65 -33 130 -43q19 -31 19 -59z" id="x2217"></path></g><g transform="matrix(.012,-0,0,-.012,11.388,17.763)"><path d="M499 88q-41 -46 -83.5 -73t-68.5 -27q-41 0 -19 98l52 225q10 43 8 59.5t-16 16.5q-37 0 -112 -65t-117 -135q-14 -42 -38 -179q-36 -7 -75 -20l-7 8l127 594q8 40 2.5 49t-35.5 9h-35l5 25q36 3 71.5 13t56.5 18t25 8q11 0 3 -38l-88 -417h2q77 102 195 167q44 24 79 24
q61 0 30 -130l-52 -220q-8 -33 4 -33q8 0 31 14.5t43 33.5z" id="x210E"></path></g>
</svg>.</table>

International Journal of Reconfigurable Computing

Reduced-Precision Redundancy on FPGAs

Figure 3